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CD74HC4017QPWRG4Q1

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Texas Instruments Counters / Dividers, TSSOP-16. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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CD74HC4017QPWRG4Q1

Texas Instruments · Counters / Dividers · TSSOP-16

CD74HC4017QPWRG4Q1 from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q5 output Decoded output 5 is normally low, goes high during clock period 5 of the ten-clock-period cycle, and is forced low by a high MR.
2 Q1 output Decoded output 1 is normally low, goes high during clock period 1 of the ten-clock-period cycle, and is forced low by a high MR.
3 Q0 output Decoded output 0 goes high during clock period 0 of the ten-clock-period cycle and is the only decoded output that MR sets high.
4 Q2 output Decoded output 2 is normally low, goes high during clock period 2 of the ten-clock-period cycle, and is forced low by a high MR.
5 Q6 output Decoded output 6 is normally low, goes high during clock period 6 of the ten-clock-period cycle, and is forced low by a high MR.
6 Q7 output Decoded output 7 is normally low, goes high during clock period 7 of the ten-clock-period cycle, and is forced low by a high MR.
7 Q3 output Decoded output 3 is normally low, goes high during clock period 3 of the ten-clock-period cycle, and is forced low by a high MR.
8 GND power_in Ground reference; all voltages are referenced to GND.
9 Q8 output Decoded output 8 is normally low, goes high during clock period 8 of the ten-clock-period cycle, and is forced low by a high MR.
10 Q4 output Decoded output 4 is normally low, goes high during clock period 4 of the ten-clock-period cycle, and is forced low by a high MR.
11 Q9 output Decoded output 9 is normally low, goes high during clock period 9 of the ten-clock-period cycle, and is forced low by a high MR.
12 TC output Carry output goes low to high after output 9 goes high to low, is high when the count n is less than 5 and low otherwise, and is used with CE to cascade stages.
13 CE input Clock enable; a high level disables counting.
14 CP input Clock input; the counter increments on the low-to-high transition when CE and MR are low (positive-edge clocking).
15 MR input Master reset; when taken high it sets output 0 high and all other decoded outputs low.
16 VCC power_in Supply voltage, 2 V to 6 V per the recommended operating conditions.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category Logic ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High-level output voltage, CMOS loads (VCC = 2 V) VOH 1.9 V CMOS loads, IO = −0.02 mA, VI = VIH or VIL, VCC = 2 V, TA = 25°C 3
High-level output voltage, CMOS loads (VCC = 4.5 V) VOH 4.4 V CMOS loads, IO = −0.02 mA, VI = VIH or VIL, VCC = 4.5 V, TA = 25°C 3
High-level output voltage, CMOS loads (VCC = 6 V) VOH 5.9 V CMOS loads, IO = −0.02 mA, VI = VIH or VIL, VCC = 6 V, TA = 25°C 3
High-level output voltage, TTL loads (VCC = 4.5 V) VOH 3.98 V TTL loads, IO = −4 mA, VI = VIH or VIL, VCC = 4.5 V, TA = 25°C 3
High-level output voltage, TTL loads (VCC = 4.5 V) VOH 3.7 V TTL loads, IO = −4 mA, VI = VIH or VIL, VCC = 4.5 V, TA = −40°C to 125°C 3
High-level output voltage, TTL loads (VCC = 6 V) VOH 5.48 V TTL loads, IO = −5.2 mA, VI = VIH or VIL, VCC = 6 V, TA = 25°C 3
High-level output voltage, TTL loads (VCC = 6 V) VOH 5.2 V TTL loads, IO = −5.2 mA, VI = VIH or VIL, VCC = 6 V, TA = −40°C to 125°C 3
Low-level output voltage, CMOS loads (VCC = 2 V) VOL 0.1 V CMOS loads, IO = 0.02 mA, VI = VIH or VIL, VCC = 2 V, TA = 25°C 3
Low-level output voltage, CMOS loads (VCC = 4.5 V) VOL 0.1 V CMOS loads, IO = 0.02 mA, VI = VIH or VIL, VCC = 4.5 V, TA = 25°C 3
Low-level output voltage, CMOS loads (VCC = 6 V) VOL 0.1 V CMOS loads, IO = 0.02 mA, VI = VIH or VIL, VCC = 6 V, TA = 25°C 3
Low-level output voltage, TTL loads (VCC = 4.5 V) VOL 0.26 V TTL loads, IO = 4 mA, VI = VIH or VIL, VCC = 4.5 V, TA = 25°C 3
Low-level output voltage, TTL loads (VCC = 4.5 V) VOL 0.4 V TTL loads, IO = 4 mA, VI = VIH or VIL, VCC = 4.5 V, TA = −40°C to 125°C 3
Low-level output voltage, TTL loads (VCC = 6 V) VOL 0.26 V TTL loads, IO = 5.2 mA, VI = VIH or VIL, VCC = 6 V, TA = 25°C 3
Low-level output voltage, TTL loads (VCC = 6 V) VOL 0.4 V TTL loads, IO = 5.2 mA, VI = VIH or VIL, VCC = 6 V, TA = −40°C to 125°C 3
Input leakage current II -0.1 0.1 µA VI = VCC or GND, VCC = 6 V, TA = 25°C 3
Input leakage current II -1 1 µA VI = VCC or GND, VCC = 6 V, TA = −40°C to 125°C 3
Quiescent supply current ICC 8 µA VI = VCC or GND, IO = 0, VCC = 6 V, TA = 25°C 3
Quiescent supply current ICC 160 µA VI = VCC or GND, IO = 0, VCC = 6 V, TA = −40°C to 125°C 3
Input capacitance CIN 10 pF CL = 50 pF, TA = 25°C 3
Supply voltage VCC 2 6 V 3
High-level input voltage VIH 1.5 V VCC = 2 V 3
High-level input voltage VIH 3.15 V VCC = 4.5 V 3
High-level input voltage VIH 4.2 V VCC = 6 V 3
Low-level input voltage VIL 0.5 V VCC = 2 V 3
Low-level input voltage VIL 1.35 V VCC = 4.5 V 3
Low-level input voltage VIL 1.8 V VCC = 6 V 3
Input voltage VI 0 V 3
Output voltage VO 0 V 3
Input transition (rise and fall) time tt 0 1000 ns VCC = 2 V 3
Input transition (rise and fall) time tt 0 500 ns VCC = 4.5 V 3
Input transition (rise and fall) time tt 0 400 ns VCC = 6 V 3
Operating free-air temperature TA -40 125 °C 3
Supply voltage range VCC -0.5 7 V see Note 1 (voltages referenced to GND) 2
Input clamp current IIK -20 20 mA VI < −0.5 V or VI > VCC + 0.5 V 2
Output clamp current IOK -20 20 mA VO < −0.5 V or VO > VCC + 0.5 V 2
Source or sink current per output pin IO -25 25 mA VO > −0.5 V or VO < VCC + 0.5 V 2
Continuous current through VCC or GND -50 50 mA 2
Package thermal impedance, PW package θJA 108 °C/W PW package, see Note 2 (JESD 51-7) 2
Maximum junction temperature TJ 150 °C 2
Lead temperature (during soldering) 300 °C 1/16 inch from case for 10 s max 2
Storage temperature range Tstg -65 150 °C 2

CAD (KiCad official)

  • Symbol: CD74HC4017QPWRG4Q1
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: cd74hc4017qpwrg4q1-etched.step / cd74hc4017qpwrg4q1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hc4017qpwrg4q1.step / cd74hc4017qpwrg4q1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (15 pp, sha256 dfb7c4361299bb41, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF