Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

CD74HC4017M96

Texas Instruments · Counters, Dividers · SOIC-16

CD74HC4017M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 5 output Decoded output 5, normally low and goes high on the fifth clock count; drives up to 10 LSTTL loads.
2 1 output Decoded output 1, normally low and goes high on the first clock count; drives up to 10 LSTTL loads.
3 0 output Decoded output 0, high after reset and when the count is zero; drives up to 10 LSTTL loads.
4 2 output Decoded output 2, normally low and goes high on the second clock count; drives up to 10 LSTTL loads.
5 6 output Decoded output 6, normally low and goes high on the sixth clock count; drives up to 10 LSTTL loads.
6 7 output Decoded output 7, normally low and goes high on the seventh clock count; drives up to 10 LSTTL loads.
7 3 output Decoded output 3, normally low and goes high on the third clock count; drives up to 10 LSTTL loads.
8 GND power_in Ground reference.
9 8 output Decoded output 8, normally low and goes high on the eighth clock count; drives up to 10 LSTTL loads.
10 4 output Decoded output 4, normally low and goes high on the fourth clock count; drives up to 10 LSTTL loads.
11 9 output Decoded output 9, normally low and goes high on the ninth clock count; drives up to 10 LSTTL loads.
12 TC output Carry (terminal count) output, high for counts 0-4 and low for 5-9, transitions low to high after output 9 goes low, used with CE to cascade stages.
13 CE input Clock enable input, disables counting when high.
14 CP input Clock input, counter increments on the low-to-high transition when CE is low and MR is low.
15 MR input Master reset input, when high sets output 0 high and all other decoded outputs low.
16 VCC power_in Positive supply voltage, 2V to 6V operating range for HC types (absolute maximum -0.5V to 7V).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: CD74HC4017M96
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: cd74hc4017m96-etched.step / cd74hc4017m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hc4017m96.step / cd74hc4017m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (20 pp, sha256 91818c8e1f5622e9, retrieved 2026-10-01, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF