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CD74HC40103QM96EP

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Texas Instruments Counters, Dividers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD74HC40103QM96EP

Texas Instruments · Counters, Dividers · SOIC-16

CD74HC40103QM96EP from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CP input Clock input; the counter decrements by one on each positive transition, with synchronous operations changing on negative-to-positive clock transitions.
2 MR input Active-low master reset that asynchronously clears the counter to its maximum count of 255 regardless of the state of any other input.
3 TE input Active-low terminal enable; counting is inhibited when TE is high, and TC goes low at zero count only when TE is low, which is used for cascading.
4 P0 input Parallel preset data input for the LSB of the 8-bit preset word, loaded on PE (synchronous) or PL (asynchronous) preset.
5 P1 input Parallel preset data input (bit 1) of the 8-bit preset word, loaded on PE (synchronous) or PL (asynchronous) preset.
6 P2 input Parallel preset data input (bit 2) of the 8-bit preset word, loaded on PE (synchronous) or PL (asynchronous) preset.
7 P3 input Parallel preset data input (bit 3) of the 8-bit preset word, loaded on PE (synchronous) or PL (asynchronous) preset.
8 GND power_in Device ground; all voltages are referenced to GND.
9 PL (ASYNC) input Active-low asynchronous preset enable that forces data at P0-P7 into the counter regardless of the state of PE, TE, or CP.
10 P4 input Parallel preset data input (bit 4) of the 8-bit preset word, loaded on PE (synchronous) or PL (asynchronous) preset.
11 P5 input Parallel preset data input (bit 5) of the 8-bit preset word, loaded on PE (synchronous) or PL (asynchronous) preset.
12 P6 input Parallel preset data input (bit 6) of the 8-bit preset word, loaded on PE (synchronous) or PL (asynchronous) preset.
13 P7 input Parallel preset data input for the MSB of the 8-bit preset word, loaded on PE (synchronous) or PL (asynchronous) preset.
14 TC output Active-low terminal count output that goes low when the count reaches zero (with TE low) and remains low for one full clock period.
15 PE (SYNC) input Active-low synchronous preset enable; when low, P0-P7 data are clocked into the counter on the next positive clock transition regardless of TE.
16 VCC power_in Supply voltage, specified from 2 V to 6 V (recommended operating range).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: CD74HC40103QM96EP
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: cd74hc40103qm96ep-etched.step / cd74hc40103qm96ep-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hc40103qm96ep.step / cd74hc40103qm96ep.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (14 pp, sha256 c47ef32a7e9ae0b2, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF