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CD74HC390M96

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Texas Instruments Logic ICs, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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CD74HC390M96

Texas Instruments · Logic ICs · SOP-16

CD74HC390M96 from Texas Instruments, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1CP0 input Clock input of the first divide-by-2 section, triggered on the High-to-Low transition.
2 1MR input Active-High asynchronous master reset for the first decade counter; a High level overrides the clock and sets its four outputs Low.
3 1Q0 output Output of the first divide-by-2 section, connected to 1CP1 for BCD decade operation or used as the decade output in bi-quinary operation.
4 1CP1 input Clock input of the first divide-by-5 section, triggered on the High-to-Low transition.
5 1Q1 output Output Q1 of the first divide-by-5 section.
6 1Q2 output Output Q2 of the first divide-by-5 section.
7 1Q3 output Output Q3 of the first divide-by-5 section, connected to 1CP0 for bi-quinary decade operation.
8 GND power_in Ground supply pin.
9 2Q3 output Output Q3 of the second divide-by-5 section, connected to 2CP0 for bi-quinary decade operation.
10 2Q2 output Output Q2 of the second divide-by-5 section.
11 2Q1 output Output Q1 of the second divide-by-5 section.
12 2CP1 input Clock input of the second divide-by-5 section, triggered on the High-to-Low transition.
13 2Q0 output Output of the second divide-by-2 section, connected to 2CP1 for BCD decade operation or used as the decade output in bi-quinary operation.
14 2MR input Active-High asynchronous master reset for the second decade counter; a High level overrides the clock and sets its four outputs Low.
15 2CP0 input Clock input of the second divide-by-2 section, triggered on the High-to-Low transition.
16 VCC power_in Positive supply pin; HC types operate from 2V to 6V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOP-16
Category Logic ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage VCC -0.5 7 V 4
DC Input Diode Current IIK -20 20 mA For VI < -0.5V or VI > VCC + 0.5V 4
DC Output Diode Current IOK -20 20 mA For VO < -0.5V or VO > VCC + 0.5V 4
DC Output Source or Sink Current per Output Pin IO -25 25 mA For VO > -0.5V or VO < VCC + 0.5V 4
DC VCC or Ground Current ICC or IGND -50 50 mA 4
Maximum Storage Temperature Range -65 150 °C 4
Maximum Junction Temperature 150 °C 4
Temperature Range TA -55 125 °C 4
Supply Voltage Range, HC Types VCC 2 6 V HC types 4
DC Input or Output Voltage VI, VO 0 V 0V to VCC 4
Input Rise and Fall Time 1000 ns VCC = 2V 4
Input Rise and Fall Time 500 ns VCC = 4.5V 4
Input Rise and Fall Time 400 ns VCC = 6V 4
High Level Input Voltage VIH 1.5 V VCC=2 V; -55 to 125°C 4
High Level Input Voltage VIH 3.15 V VCC=4.5 V; -55 to 125°C 4
High Level Input Voltage VIH 4.2 V VCC=6 V; -55 to 125°C 4
Low Level Input Voltage VIL 0.5 V VCC=2 V; -55 to 125°C 4
Low Level Input Voltage VIL 1.35 V VCC=4.5 V; -55 to 125°C 4
Low Level Input Voltage VIL 1.8 V VCC=6 V; -55 to 125°C 4
High Level Output Voltage CMOS Loads VOH 1.9 V VI=VIH or VIL; IO=-0.02 mA; VCC=2 V; -55 to 125°C 4
High Level Output Voltage CMOS Loads VOH 4.4 V VI=VIH or VIL; IO=-0.02 mA; VCC=4.5 V; -55 to 125°C 4
High Level Output Voltage CMOS Loads VOH 5.9 V VI=VIH or VIL; IO=-0.02 mA; VCC=6 V; -55 to 125°C 4
High Level Output Voltage TTL Loads VOH 3.7 V IO=-4 mA; VCC=4.5 V; -55 to 125°C 4
High Level Output Voltage TTL Loads VOH 5.2 V IO=-5.2 mA; VCC=6 V; -55 to 125°C 4
Low Level Output Voltage CMOS Loads VOL 0.1 V VI=VIH or VIL; IO=0.02 mA; VCC=2 V; -55 to 125°C 4
Low Level Output Voltage TTL Loads VOL 0.4 V IO=4 mA; VCC=4.5 V; -55 to 125°C 4
Input Leakage Current II -1 1 µA VI=VCC or GND; VCC=6 V; -55 to 125°C 4
Quiescent Device Current ICC 160 µA VI=VCC or GND; IO=0; VCC=6 V; -55 to 125°C 4
Maximum Clock Frequency fMAX 4 MHz VCC=2 V; -55 to 125°C 5
Maximum Clock Frequency fMAX 20 MHz VCC=4.5 V; -55 to 125°C 5
Maximum Clock Frequency fMAX 24 MHz VCC=6 V; -55 to 125°C 5
Clock Pulse Width nCP0, nCP1 tW 120 ns VCC=2 V; -55 to 125°C 5
Clock Pulse Width nCP0, nCP1 tW 24 ns VCC=4.5 V; -55 to 125°C 5
Clock Pulse Width nCP0, nCP1 tW 20 ns VCC=6 V; -55 to 125°C 5
Reset Removal Time tREM 105 ns VCC=2 V; -55 to 125°C 6
Reset Removal Time tREM 21 ns VCC=4.5 V; -55 to 125°C 6
Reset Removal Time tREM 18 ns VCC=6 V; -55 to 125°C 6
Reset Pulse Width tW 75 ns VCC=2 V; -55 to 125°C 6
Reset Pulse Width tW 15 ns VCC=4.5 V; -55 to 125°C 6
Reset Pulse Width tW 13 ns VCC=6 V; -55 to 125°C 6
Propagation Delay nCP0 to nQ0 tPLH, tPHL 265 ns CL = 50pF; VCC=2 V; -55 to 125°C 6
Propagation Delay nCP0 to nQ0 tPLH, tPHL 53 ns CL = 50pF; VCC=4.5 V; -55 to 125°C 6
Propagation Delay nCP0 to nQ0 tPLH, tPHL 45 ns CL = 50pF; VCC=6 V; -55 to 125°C 6
Propagation Delay nCP1 to nQ1 tPLH, tPHL 280 ns CL = 50pF; VCC=2 V; -55 to 125°C 6
Propagation Delay nCP1 to nQ1 tPLH, tPHL 56 ns CL = 50pF; VCC=4.5 V; -55 to 125°C 6
Propagation Delay nCP1 to nQ1 tPLH, tPHL 48 ns CL = 50pF; VCC=6 V; -55 to 125°C 6
Propagation Delay nCP1 to nQ2 tPLH, tPHL 370 ns CL = 50pF; VCC=2 V; -55 to 125°C 6
Propagation Delay nCP1 to nQ2 tPLH, tPHL 74 ns CL = 50pF; VCC=4.5 V; -55 to 125°C 6
Propagation Delay nCP1 to nQ2 tPLH, tPHL 63 ns CL = 50pF; VCC=6 V; -55 to 125°C 6
Propagation Delay nCP1 to nQ3 tPLH, tPHL 270 ns CL = 50pF; VCC=2 V; -55 to 125°C 6
Propagation Delay nCP1 to nQ3 tPLH, tPHL 54 ns CL = 50pF; VCC=4.5 V; -55 to 125°C 6
Propagation Delay nCP1 to nQ3 tPLH, tPHL 46 ns CL = 50pF; VCC=6 V; -55 to 125°C 6
Propagation Delay MR to Qn tPLH, tPHL 285 ns CL = 50pF; VCC=2 V; -55 to 125°C 6
Propagation Delay MR to Qn tPLH, tPHL 57 ns CL = 50pF; VCC=4.5 V; -55 to 125°C 6
Propagation Delay MR to Qn tPLH, tPHL 48 ns CL = 50pF; VCC=6 V; -55 to 125°C 6
Input Capacitance CIN 10 pF CL = 50pF; -55 to 125°C 7
Thermal Resistance Junction to Ambient, M (SOIC) Package θJA 73 °C/W Typical, Note 1 (JESD 51-7) 4

CAD (KiCad official)

  • Symbol: CD74HC390M96
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: cd74hc390m96-etched.step / cd74hc390m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hc390m96.step / cd74hc390m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (16 pp, sha256 22c6410e118bc3aa, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF