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CD74HC221M96

Public Made by Adom

by adom

Texas Instruments Monostable Multivibrators, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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docs cd74hc221m96: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers cd74hc221m96: viewers · Ray
cd74hc221m96-etched.fit.json cd74hc221m96: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd74hc221m96-etched.glb cd74hc221m96: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC bod… · Ray
cd74hc221m96-etched.step cd74hc221m96: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC bod… · Ray
cd74hc221m96.glb Publish 0.1.0 · Ray
cd74hc221m96.kicad_mod Publish 0.1.0 · Ray
cd74hc221m96.kicad_sym Publish 0.1.0 · Ray
cd74hc221m96.lbr Publish 0.1.0 · Ray
cd74hc221m96.step Publish 0.1.0 · Ray
package.json cd74hc221m96: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC bod… · Ray
page.json cd74hc221m96: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC bod… · Ray
README.md Initial commit: component/cd74hc221m96 · Ray

CD74HC221M96

Texas Instruments · Monostable Multivibrators · SOIC-16

CD74HC221M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Trailing-edge (active-LOW falling) trigger input for monostable 1; triggers on HIGH-to-LOW transition when 1B is HIGH and 1R is HIGH.
2 1B input Leading-edge (active-HIGH rising) Schmitt-trigger input for monostable 1; triggers on LOW-to-HIGH transition when 1A is LOW and 1R is HIGH; rise/fall time unlimited.
3 1R input Active-LOW overriding reset input for monostable 1; a LOW level immediately terminates the output pulse, forcing 1Q LOW and 1Q̄ HIGH; minimum pulse width 14 ns at 4.5 V.
4 1Q̄ output Buffered complementary output of monostable 1; idles HIGH, pulses LOW for tW = 0.7 × RX × CX; VOH ≥ 4.4 V and VOL ≤ 0.1 V at VCC = 4.5 V, IO = ±0.02 mA.
5 2Q output Buffered true output of monostable 2; idles LOW, pulses HIGH for tW = 0.7 × RX × CX; VOH ≥ 4.4 V and VOL ≤ 0.1 V at VCC = 4.5 V, IO = ±0.02 mA.
6 2CX passive External timing capacitor (CX) connection for monostable 2; CX is connected between this pin and GND; minimum CX = 0 pF.
7 2CXRX passive External timing resistor-capacitor junction for monostable 2; RX connected between this pin and VCC, CX between pin 6 and GND; minimum RX = 500 Ω typical.
8 GND power_in Ground (0 V) supply reference; maximum DC VCC or ground current ICC = ±50 mA.
9 2A input Trailing-edge (active-LOW falling) trigger input for monostable 2; triggers on HIGH-to-LOW transition when 2B is HIGH and 2R is HIGH.
10 2B input Leading-edge (active-HIGH rising) Schmitt-trigger input for monostable 2; triggers on LOW-to-HIGH transition when 2A is LOW and 2R is HIGH; rise/fall time unlimited.
11 2R input Active-LOW overriding reset input for monostable 2; a LOW level immediately terminates the output pulse, forcing 2Q LOW and 2Q̄ HIGH; minimum pulse width 14 ns at 4.5 V.
12 2Q̄ output Buffered complementary output of monostable 2; idles HIGH, pulses LOW for tW = 0.7 × RX × CX; VOH ≥ 4.4 V and VOL ≤ 0.1 V at VCC = 4.5 V, IO = ±0.02 mA.
13 1Q output Buffered true output of monostable 1; idles LOW, pulses HIGH for tW = 0.7 × RX × CX; VOH ≥ 4.4 V and VOL ≤ 0.1 V at VCC = 4.5 V, IO = ±0.02 mA.
14 1CX passive External timing capacitor (CX) connection for monostable 1; CX is connected between this pin and GND; minimum CX = 0 pF.
15 1CXRX passive External timing resistor-capacitor junction for monostable 1; RX connected between this pin and VCC, CX between pin 14 and GND; minimum RX = 500 Ω typical.
16 VCC power_in Positive supply voltage; HC type 2 V to 6 V operating range, absolute maximum −0.5 V to 7 V; quiescent ICC ≤ 8 µA typical at 6 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: CD74HC221M96
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: cd74hc221m96-etched.step / cd74hc221m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hc221m96.step / cd74hc221m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 7f1f24f5229cfed7, retrieved 2026-09-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF