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CD74HC20M96

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Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogiccd74hc20m96factory-2.0.0extractor-text

Verified CD74HC20M96

by Ray · last 6 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

6 Nov 2026RayPublished by the parts factory: tier mfr, 14 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CD74HC20M96 · SOIC-14 · 14 pins
  • ✓copper: 14 copper pads, none touching another net
  • ✓datasheet: all 14 pin names found in the 27-page datasheet
  • ✓distributor: lcsc C2878694, digikey 296-38700-2-ND, mouser 595-CD74HC20M96
  • ✓family: SOIC-14_3.9x8.7mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-kz265sko/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 14 pins = 14 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 14 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cd74hc20m96.kicad_sym✓ cd74hc20m96.kicad_mod✓ cd74hc20m96.step
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CD74HC20M96

Texas Instruments · Logic Gates · SOIC-14

CD74HC20M96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Input A of the first 4-input NAND gate (Channel 1), one of four inputs whose logic-high level sets the output with the other inputs.
2 1B input Input B of the first 4-input NAND gate (Channel 1).
3 NC unconnected Not internally connected; pin 3 is listed as NC in the pin function table.
4 1C input Input C of the first 4-input NAND gate (Channel 1).
5 1D input Input D of the first 4-input NAND gate (Channel 1).
6 1Y output Output Y of the first NAND gate (Channel 1), implementing Y = A ● B ● C ● D in positive logic.
7 GND power_in Ground reference for the device.
8 2Y output Output Y of the second NAND gate (Channel 2), implementing Y = A ● B ● C ● D in positive logic.
9 2A input Input A of the second 4-input NAND gate (Channel 2).
10 2B input Input B of the second 4-input NAND gate (Channel 2).
11 NC unconnected Not internally connected; pin 11 is listed as NC in the pin function table.
12 2C input Input C of the second 4-input NAND gate (Channel 2).
13 2D input Input D of the second 4-input NAND gate (Channel 2).
14 VCC power_in Positive supply; the recommended supply range is 2 V to 6 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V over operating free-air temperature range 4
Input clamp current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 4
Output clamp current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 4
Continuous output current IO -25 25 mA VO > -0.5 V or VO < VCC + 0.5 V 4
Continuous current through VCC or GND -50 50 mA 4
Junction temperature TJ 150 °C 4
Lead temperature (soldering 10s) 300 °C SOIC - lead tips only 4
Storage temperature Tstg -65 150 °C 4
Supply voltage VCC 2 5 6 V over operating free-air temperature range 4
High-level input voltage VIH 1.5 V VCC = 2 V 4
High-level input voltage VIH 3.15 V VCC = 4.5 V 4
High-level input voltage VIH 4.2 V VCC = 6 V 4
Low-level input voltage VIL 0.5 V VCC = 2 V 4
Low-level input voltage VIL 1.35 V VCC = 4.5 V 4
Low-level input voltage VIL 1.8 V VCC = 6 V 4
Input transition time tt 1000 ns VCC = 2 V 4
Input transition time tt 500 ns VCC = 4.5 V 4
Input transition time tt 400 ns VCC = 6 V 4
Operating free-air temperature TA -55 125 °C 4
Junction-to-ambient thermal resistance (D, SOIC-14) RθJA 133.6 °C/W 5
Junction-to-case (top) thermal resistance (D, SOIC-14) RθJC(top) 89 °C/W 5
Junction-to-board thermal resistance (D, SOIC-14) RθJB 89.5 °C/W 5
Junction-to-top characterization parameter (D, SOIC-14) ΨJT 45.5 °C/W 5
Junction-to-board characterization parameter (D, SOIC-14) ΨJB 89.1 °C/W 5
High-level output voltage VOH 1.9 V VI = VIH or VIL; IOH = -20 µA; VCC = 2 V; TA = -55°C to 125°C 5
High-level output voltage VOH 4.4 V VI = VIH or VIL; IOH = -20 µA; VCC = 4.5 V; TA = -55°C to 125°C 5
High-level output voltage VOH 5.9 V VI = VIH or VIL; IOH = -20 µA; VCC = 6 V; TA = -55°C to 125°C 5
High-level output voltage VOH 3.7 V VI = VIH or VIL; IOH = -4 mA; VCC = 4.5 V; TA = -55°C to 125°C 5
High-level output voltage VOH 5.2 V VI = VIH or VIL; IOH = -5.2 mA; VCC = 6 V; TA = -55°C to 125°C 5
Low-level output voltage VOL 0.1 V VI = VIH or VIL; IOL = 20 µA; VCC = 2 V; TA = -55°C to 125°C 5
Low-level output voltage VOL 0.4 V VI = VIH or VIL; IOL = 4 mA; VCC = 4.5 V; TA = -55°C to 125°C 5
Input leakage current II -1 1 µA VI = VCC or GND; VCC = 6 V; TA = -55°C to 125°C 5
Supply current ICC 40 µA VI = VCC or GND; IO = 0; VCC = 6 V; TA = -55°C to 125°C 5
Propagation delay A, B, C, or D to Y tpd 150 ns CL = 50 pF; VCC = 2 V; TA = -55°C to 125°C 5
Propagation delay A, B, C, or D to Y tpd 30 ns CL = 50 pF; VCC = 4.5 V; TA = -55°C to 125°C 5
Propagation delay A, B, C, or D to Y tpd 26 ns CL = 50 pF; VCC = 6 V; TA = -55°C to 125°C 5
Transition time Y tt 110 ns CL = 50 pF; VCC = 2 V; TA = -55°C to 125°C 6
Transition time Y tt 22 ns CL = 50 pF; VCC = 4.5 V; TA = -55°C to 125°C 6
Transition time Y tt 19 ns CL = 50 pF; VCC = 6 V; TA = -55°C to 125°C 6

CAD (KiCad official)

  • Symbol: CD74HC20M96
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: cd74hc20m96-etched.step / cd74hc20m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hc20m96.step / cd74hc20m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (27 pp, sha256 bb9f9a152deb8f68, retrieved 2026-11-06, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF