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CD74HC192NSR

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Texas Instruments Counters, Dividers, SO-16-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD74HC192NSR

Texas Instruments · Counters, Dividers · SO-16-208mil

CD74HC192NSR from Texas Instruments, in a SO-16-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P1 input Preset data input 1 loaded into the counter when PL is low.
2 Q1 output Counter output bit 1, bus driver output.
3 Q0 output Counter output bit 0 (LSB).
4 CPD input Clock-Down input; count decrements on low-to-high transition while Clock-Up is high.
5 CPU input Clock-Up input; count increments on low-to-high transition while Clock-Down is high.
6 Q2 output Counter output bit 2.
7 Q3 output Counter output bit 3 (MSB).
8 GND power_in Ground pin.
9 P3 input Preset data input 3 loaded into the counter when PL is low.
10 P2 input Preset data input 2 loaded into the counter when PL is low.
11 PL input Active-low asynchronous parallel load input that presets the counter to P0-P3.
12 TCU output Terminal Count Up (carry) output, goes low half a clock period before the zero count and returns high at zero count.
13 TCD output Terminal Count Down (borrow) output, goes low half a clock period before the maximum count (9 in the 192) and returns high at maximum count.
14 MR input Master reset; a high level overrides all other inputs and clears the counter to zero.
15 P0 input Preset data input 0 loaded into the counter when PL is low.
16 VCC power_in Positive supply voltage, 2V to 6V for HC types.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SO-16-208mil
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High Level Input Voltage VIH 1.5 V VCC=2 V; -55 to 125 °C 3
High Level Input Voltage VIH 3.15 V VCC=4.5 V; -55 to 125 °C 3
High Level Input Voltage VIH 4.2 V VCC=6 V; -55 to 125 °C 3
Low Level Input Voltage VIL 0.5 V VCC=2 V; -55 to 125 °C 3
Low Level Input Voltage VIL 1.35 V VCC=4.5 V; -55 to 125 °C 3
Low Level Input Voltage VIL 1.8 V VCC=6 V; -55 to 125 °C 3
High Level Output Voltage, CMOS Loads VOH 1.9 V VI=VIH or VIL; IO=-0.02 mA; VCC=2 V; -55 to 125 °C 3
High Level Output Voltage, CMOS Loads VOH 4.4 V VI=VIH or VIL; IO=-0.02 mA; VCC=4.5 V; -55 to 125 °C 3
High Level Output Voltage, CMOS Loads VOH 5.9 V VI=VIH or VIL; IO=-0.02 mA; VCC=6 V; -55 to 125 °C 3
High Level Output Voltage, TTL Loads VOH 3.7 V IO=-4 mA; VCC=4.5 V; -55 to 125 °C 3
High Level Output Voltage, TTL Loads VOH 5.2 V IO=-5.2 mA; VCC=6 V; -55 to 125 °C 3
Low Level Output Voltage, CMOS Loads VOL 0.1 V VI=VIH or VIL; IO=0.02 mA; VCC=2 V; -55 to 125 °C 3
Low Level Output Voltage, TTL Loads VOL 0.4 V IO=4 mA; VCC=4.5 V; -55 to 125 °C 3
Input Leakage Current II -1 1 µA VI=VCC or GND; VCC=6 V; -55 to 125 °C 3
Quiescent Device Current ICC 160 µA VI=VCC or GND; IO=0; VCC=6 V; -55 to 125 °C 3
Temperature Range TA -55 125 °C 3
Supply Voltage Range, HC Types VCC 2 6 V HC types 3
Input Rise and Fall Time 1000 ns VCC=2 V 3
Input Rise and Fall Time 500 ns VCC=4.5 V 3
Input Rise and Fall Time 400 ns VCC=6 V 3
DC Input or Output Voltage VI, VO 0 V Upper limit is VCC 3
DC Supply Voltage VCC -0.5 7 V 3
DC Input Diode Current IIK -20 20 mA For VI < -0.5 V or VI > VCC + 0.5 V 3
DC Output Diode Current IOK -20 20 mA For VO < -0.5 V or VO > VCC + 0.5 V 3
DC Output Source or Sink Current per Output Pin IO -25 25 mA For VO > -0.5 V or VO < VCC + 0.5 V 3
DC VCC or Ground Current ICC, IGND -50 50 mA 3
Maximum Junction Temperature 150 °C 3
Maximum Storage Temperature Range -65 150 °C 3
Maximum Lead Temperature (Soldering 10 s) 300 °C SOIC lead tips only 3
Maximum Frequency, CPU, CPD (192) fMAX 3 MHz VCC=2 V; -55 to 125 °C 5
Maximum Frequency, CPU, CPD (192) fMAX 15 MHz VCC=4.5 V; -55 to 125 °C 5
Maximum Frequency, CPU, CPD (192) fMAX 18 MHz VCC=6 V; -55 to 125 °C 5
Propagation Delay CPU to TCU tPLH, tPHL 190 ns CL=50 pF; VCC=2 V; input tr, tf=6 ns; -55 to 125 °C 6
Propagation Delay CPU to TCU tPLH, tPHL 38 ns CL=50 pF; VCC=4.5 V; input tr, tf=6 ns; -55 to 125 °C 6
Propagation Delay CPU to TCU tPLH, tPHL 32 ns CL=50 pF; VCC=6 V; input tr, tf=6 ns; -55 to 125 °C 6
Propagation Delay CPD to TCD tPLH, tPHL 190 ns CL=50 pF; VCC=2 V; input tr, tf=6 ns; -55 to 125 °C 6
Propagation Delay CPD to TCD tPLH, tPHL 38 ns CL=50 pF; VCC=4.5 V; input tr, tf=6 ns; -55 to 125 °C 6
Propagation Delay CPD to TCD tPLH, tPHL 32 ns CL=50 pF; VCC=6 V; input tr, tf=6 ns; -55 to 125 °C 6
Propagation Delay CPU to Qn tPLH, tPHL 325 ns CL=50 pF; VCC=2 V; input tr, tf=6 ns; -55 to 125 °C 6
Propagation Delay CPU to Qn tPLH, tPHL 65 ns CL=50 pF; VCC=4.5 V; input tr, tf=6 ns; -55 to 125 °C 6
Propagation Delay CPU to Qn tPLH, tPHL 55 ns CL=50 pF; VCC=6 V; input tr, tf=6 ns; -55 to 125 °C 6
Propagation Delay CPD to Qn tPLH, tPHL 325 ns CL=50 pF; VCC=2 V; input tr, tf=6 ns; -55 to 125 °C 7
Propagation Delay CPD to Qn tPLH, tPHL 65 ns CL=50 pF; VCC=4.5 V; input tr, tf=6 ns; -55 to 125 °C 7
Propagation Delay CPD to Qn tPLH, tPHL 55 ns CL=50 pF; VCC=6 V; input tr, tf=6 ns; -55 to 125 °C 7
Propagation Delay PL to Qn tPLH, tPHL 330 ns CL=50 pF; VCC=2 V; input tr, tf=6 ns; -55 to 125 °C 7
Propagation Delay PL to Qn tPLH, tPHL 66 ns CL=50 pF; VCC=4.5 V; input tr, tf=6 ns; -55 to 125 °C 7
Propagation Delay PL to Qn tPLH, tPHL 56 ns CL=50 pF; VCC=6 V; input tr, tf=6 ns; -55 to 125 °C 7
Propagation Delay MR to Qn tPHL 300 ns CL=50 pF; VCC=2 V; input tr, tf=6 ns; -55 to 125 °C 7
Propagation Delay MR to Qn tPHL 60 ns CL=50 pF; VCC=4.5 V; input tr, tf=6 ns; -55 to 125 °C 7
Propagation Delay MR to Qn tPHL 51 ns CL=50 pF; VCC=6 V; input tr, tf=6 ns; -55 to 125 °C 7
Transition Time Q, TCU, TCD tTLH, tTHL 110 ns CL=50 pF; VCC=2 V; -55 to 125 °C 7
Transition Time Q, TCU, TCD tTLH, tTHL 22 ns CL=50 pF; VCC=4.5 V; -55 to 125 °C 7
Transition Time Q, TCU, TCD tTLH, tTHL 19 ns CL=50 pF; VCC=6 V; -55 to 125 °C 7
Pulse Width CPU, CPD (192) tW 175 ns VCC=2 V; -55 to 125 °C 5
Pulse Width CPU, CPD (192) tW 35 ns VCC=4.5 V; -55 to 125 °C 5
Pulse Width CPU, CPD (192) tW 30 ns VCC=6 V; -55 to 125 °C 5
Package Thermal Impedance, NS (SOP) package θJA 64 °C/W Per JESD 51-7 3

CAD (KiCad official)

  • Symbol: CD74HC192NSR
  • Footprint: Adom_Gen:Texas_Instruments_CD74
  • 3D model: SO-16-208mil (KiCad packages3D, STEP)
  • 3D model files: cd74hc192nsr-etched.step / cd74hc192nsr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hc192nsr.step / cd74hc192nsr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (27 pp, sha256 eec28d8331d25038, retrieved 2026-10-21, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF