CD74HC166M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SER	input	Serial data input that feeds the first register stage when shift mode is selected (SH/LD high).
2	A	input	Parallel data input A, loaded into the register when SH/LD is low on a rising clock edge.
3	B	input	Parallel data input B, loaded into the register when SH/LD is low on a rising clock edge.
4	C	input	Parallel data input C, loaded into the register when SH/LD is low on a rising clock edge.
5	D	input	Parallel data input D, loaded into the register when SH/LD is low on a rising clock edge.
6	CLK INH	input	Clock inhibit input, which is one input of the gated OR clock structure; when high it holds the register state.
7	CLK	input	Clock input, which shifts or loads data on the low-to-high transition and is gated OR with CLK INH.
8	GND	power_in	Ground reference for the device.
9	CLR	input	Active-low asynchronous clear that overrides all other inputs and forces all register bits low.
10	E	input	Parallel data input E, loaded into the register when SH/LD is low on a rising clock edge.
11	F	input	Parallel data input F, loaded into the register when SH/LD is low on a rising clock edge.
12	G	input	Parallel data input G, loaded into the register when SH/LD is low on a rising clock edge.
13	QH	output	Serial output from the last (eighth) register stage, which can drive the SER input of a following stage for expansion.
14	H	input	Parallel data input H, loaded into the register when SH/LD is low on a rising clock edge.
15	SH/LD	input	Shift/load control input that selects parallel load when low and serial shift when high.
16	VCC	power_in	Positive supply; recommended operating range is 2 V to 6 V for HC types, with a 0.1-µF bypass capacitor recommended.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-16
Category	Logic
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage range (HC types)	VCC	2		6	V	HC types	4
Input rise and fall time	tt			1000	ns	VCC = 2 V	4
Input rise and fall time	tt			500	ns	VCC = 4.5 V	4
Input rise and fall time	tt			400	ns	VCC = 6 V	4
Temperature range	TA	-55		125	°C		4
Supply voltage	VCC	-0.5		7	V		4
Input diode current	IIK	-20		20	mA	For VI < -0.5 V or VI > VCC + 0.5 V	4
Output diode current	IOK	-20		20	mA	For VO < -0.5 V or VO > VCC + 0.5 V	4
Drain current, per output	IO	-25		25	mA	For -0.5 V < VO < VCC + 0.5 V	4
Output source or sink current per output pin	IO	-25		25	mA	For VO > -0.5 V or VO < VCC + 0.5 V	4
Continuous current through VCC or GND		-50		50	mA		4
Junction temperature	TJ			150	°C		4
Storage temperature range	Tstg	-65		150	°C		4
Lead temperature (soldering 10 s)				300	°C	SOIC lead tips only	4
Junction-to-ambient thermal resistance	RθJA		73		°C/W	D (SOIC) 16 pins	4
High level input voltage	VIH	1.5			V	VCC = 2 V	5
High level input voltage	VIH	3.15			V	VCC = 4.5 V	5
High level input voltage	VIH	4.2			V	VCC = 6 V	5
Low level input voltage	VIL			0.5	V	VCC = 2 V	5
Low level input voltage	VIL			1.35	V	VCC = 4.5 V	5
Low level input voltage	VIL			1.8	V	VCC = 6 V	5
High level output voltage	VOH	1.9			V	IOH = -20 μA, VCC = 2 V	5
High level output voltage	VOH	4.4			V	IOH = -20 μA, VCC = 4.5 V	5
High level output voltage	VOH	5.9			V	IOH = -20 μA, VCC = 6 V	5
High level output voltage	VOH	3.98			V	IOH = -4 mA, VCC = 4.5 V	5
High level output voltage	VOH	5.48			V	IOH = -5.2 mA, VCC = 6 V	5
Low level output voltage	VOL			0.1	V	IOL = 20 μA, VCC = 2 V	5
Low level output voltage	VOL			0.26	V	IOL = 4 mA, VCC = 4.5 V	5
Input leakage current	II	-0.1		0.1	μA	VI = VCC or GND, VCC = 6 V	5
Supply current	ICC			8	μA	VI = VCC or GND, VCC = 6 V	5
Clock frequency	fMAX	6			MHz	VCC = 2 V	6
Clock frequency	fMAX	30			MHz	VCC = 4.5 V	6
Clock frequency	fMAX	35			MHz	VCC = 6 V	6
MR pulse width	tw	100			ns	VCC = 2 V	6
MR pulse width	tw	20			ns	VCC = 4.5 V	6
MR pulse width	tw	17			ns	VCC = 6 V	6
Clock pulse width	tW	80			ns	VCC = 2 V	6
Clock pulse width	tW	16			ns	VCC = 4.5 V	6
Clock pulse width	tW	14			ns	VCC = 6 V	6
Set-up time data and CE to clock	tSU	80			ns	VCC = 2 V	6
Set-up time data and CE to clock	tSU	16			ns	VCC = 4.5 V	6
Set-up time data and CE to clock	tSU	14			ns	VCC = 6 V	6
Hold time data to clock	tH	1			ns	VCC = 2 V	6
Set-up time PE to CP	tSU	145			ns	VCC = 2 V	6
Set-up time PE to CP	tSU	29			ns	VCC = 4.5 V	6
Set-up time PE to CP	tSU	25			ns	VCC = 6 V	6
Clock to output propagation delay	tpd			160	ns	VCC = 2 V, tr, tf = 6 ns, CL = 50 pF	7
Clock to output propagation delay	tpd		13	32	ns	VCC = 4.5 V, CL = 15 pF	7
Clock to output propagation delay	tpd			27	ns	VCC = 6 V, tr, tf = 6 ns, CL = 50 pF	7

CAD (KiCad official)

Symbol: CD74HC166M96
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)
3D model files: cd74hc166m96-etched.step / cd74hc166m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hc166m96.step / cd74hc166m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (22 pp, sha256 4e5f01bc8e28c629, retrieved 2026-11-06, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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CD74HC166M96

Verified CD74HC166M96

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3D Model

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