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CD74HC163M96

Public Made by Adom

by adom

Texas Instruments Counters, Dividers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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docs cd74hc163m96: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers cd74hc163m96: viewers · Ray
cd74hc163m96-etched.fit.json cd74hc163m96: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd74hc163m96-etched.glb cd74hc163m96: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd74hc163m96-etched.step cd74hc163m96: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd74hc163m96.glb Publish 0.1.0 · Ray
cd74hc163m96.kicad_mod Publish 0.1.0 · Ray
cd74hc163m96.kicad_sym Publish 0.1.0 · Ray
cd74hc163m96.lbr Publish 0.1.0 · Ray
cd74hc163m96.step Publish 0.1.0 · Ray
package.json cd74hc163m96: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
page.json cd74hc163m96: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md Initial commit: component/cd74hc163m96 · Ray

CD74HC163M96

Texas Instruments · Counters, Dividers · SOIC-16

CD74HC163M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MR input Master Reset (active-low synchronous reset for HC163); MR must be low one setup time before the rising clock edge to synchronously clear all outputs to low.
2 CP input Clock input; counting and parallel loading are accomplished synchronously on the negative-to-positive (low-to-high) transition of CP; maximum frequency 30 MHz (min) at VCC = 4.5 V.
3 P0 input Parallel data input bit 0; loaded into counter on rising CP edge when SPE is low; input unit load 0.25 for HCT types.
4 P1 input Parallel data input bit 1; loaded into counter on rising CP edge when SPE is low; input unit load 0.25 for HCT types.
5 P2 input Parallel data input bit 2; loaded into counter on rising CP edge when SPE is low; input unit load 0.25 for HCT types.
6 P3 input Parallel data input bit 3; loaded into counter on rising CP edge when SPE is low; input unit load 0.25 for HCT types.
7 PE input Count Enable Parallel input; both PE and TE must be high to enable counting; high-to-low transition of PE should only occur while CP is high; input unit load 0.65 for HCT types.
8 GND power_in Ground supply reference; DC VCC or ground current ICC rated ±50 mA maximum.
9 SPE input Synchronous Parallel Enable (active-low); when low, disables counting and allows P0-P3 data to be loaded on the next rising CP edge; setup time 12 ns min at VCC = 4.5 V; input unit load 0.5 for HCT types.
10 TE input Count Enable Trickle input; both PE and TE must be high to count; TE is gated with Q0-Q3 to drive TC high at terminal count; input unit load 1.05 for HCT types.
11 Q3 output Counter output bit 3 (MSB); updated synchronously on rising CP edge; VOH ≥ 3.98 V at IO = −4 mA, VCC = 4.5 V; drives 10 LSTTL loads standard or 15 LSTTL loads bus-driver.
12 Q2 output Counter output bit 2; updated synchronously on rising CP edge; VOH ≥ 3.98 V at IO = −4 mA, VCC = 4.5 V; propagation delay CP-to-Qn 37 ns max at VCC = 4.5 V, 25 °C.
13 Q1 output Counter output bit 1; updated synchronously on rising CP edge; VOL ≤ 0.26 V at IO = 4 mA, VCC = 4.5 V.
14 Q0 output Counter output bit 0 (LSB); updated synchronously on rising CP edge; VOH ≥ 3.98 V at IO = −4 mA, VCC = 4.5 V.
15 TC output Terminal Count (look-ahead carry) output; goes high for one clock period when TE is high and counter reaches maximum count (HHHH); propagation delay CP-to-TC 37 ns max at VCC = 4.5 V, 25 °C; used to enable next cascaded stage.
16 VCC power_in Positive supply voltage; HC types: 2 V to 6 V operating range; absolute maximum −0.5 V to 7 V; ICC quiescent ≤ 8 µA typical at VCC = 6 V, 25 °C.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: CD74HC163M96
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: cd74hc163m96-etched.step / cd74hc163m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hc163m96.step / cd74hc163m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (20 pp, sha256 cfdc63695252f714, retrieved 2026-09-26, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF