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CD74HC163M96
Public Made by Adomby adom
Texas Instruments Counters, Dividers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# CD74HC163M96++**Texas Instruments** · Counters, Dividers · SOIC-16++CD74HC163M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | MR | input | Master Reset (active-low synchronous reset for HC163); MR must be low one setup time before the rising clock edge to synchronously clear all outputs to low. |+| 2 | CP | input | Clock input; counting and parallel loading are accomplished synchronously on the negative-to-positive (low-to-high) transition of CP; maximum frequency 30 MHz (min) at VCC = 4.5 V. |+| 3 | P0 | input | Parallel data input bit 0; loaded into counter on rising CP edge when SPE is low; input unit load 0.25 for HCT types. |+| 4 | P1 | input | Parallel data input bit 1; loaded into counter on rising CP edge when SPE is low; input unit load 0.25 for HCT types. |+| 5 | P2 | input | Parallel data input bit 2; loaded into counter on rising CP edge when SPE is low; input unit load 0.25 for HCT types. |+| 6 | P3 | input | Parallel data input bit 3; loaded into counter on rising CP edge when SPE is low; input unit load 0.25 for HCT types. |+| 7 | PE | input | Count Enable Parallel input; both PE and TE must be high to enable counting; high-to-low transition of PE should only occur while CP is high; input unit load 0.65 for HCT types. |+| 8 | GND | power_in | Ground supply reference; DC VCC or ground current ICC rated ±50 mA maximum. |+| 9 | SPE | input | Synchronous Parallel Enable (active-low); when low, disables counting and allows P0-P3 data to be loaded on the next rising CP edge; setup time 12 ns min at VCC = 4.5 V; input unit load 0.5 for HCT types. |+| 10 | TE | input | Count Enable Trickle input; both PE and TE must be high to count; TE is gated with Q0-Q3 to drive TC high at terminal count; input unit load 1.05 for HCT types. |+| 11 | Q3 | output | Counter output bit 3 (MSB); updated synchronously on rising CP edge; VOH ≥ 3.98 V at IO = −4 mA, VCC = 4.5 V; drives 10 LSTTL loads standard or 15 LSTTL loads bus-driver. |+| 12 | Q2 | output | Counter output bit 2; updated synchronously on rising CP edge; VOH ≥ 3.98 V at IO = −4 mA, VCC = 4.5 V; propagation delay CP-to-Qn 37 ns max at VCC = 4.5 V, 25 °C. |+| 13 | Q1 | output | Counter output bit 1; updated synchronously on rising CP edge; VOL ≤ 0.26 V at IO = 4 mA, VCC = 4.5 V. |+| 14 | Q0 | output | Counter output bit 0 (LSB); updated synchronously on rising CP edge; VOH ≥ 3.98 V at IO = −4 mA, VCC = 4.5 V. |+| 15 | TC | output | Terminal Count (look-ahead carry) output; goes high for one clock period when TE is high and counter reaches maximum count (HHHH); propagation delay CP-to-TC 37 ns max at VCC = 4.5 V, 25 °C; used to enable next cascaded stage. |+| 16 | VCC | power_in | Positive supply voltage; HC types: 2 V to 6 V operating range; absolute maximum −0.5 V to 7 V; ICC quiescent ≤ 8 µA typical at VCC = 6 V, 25 °C. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `CD74HC163M96`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)+- 3D model files: `cd74hc163m96-etched.step` / `cd74hc163m96-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74hc163m96.step` / `cd74hc163m96.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd74hc161) (20 pp, sha256 `cfdc63695252f714`, retrieved 2026-09-26, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd74hc163m96-datasheet.pdf)
page.jsonadded+204@@ -0,0 +1,204 @@+{+ "slug": "cd74hc163m96",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Counters, Dividers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "cd74hc163m96",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cd74hc163m96.kicad_sym",+ "cd74hc163m96.kicad_mod",+ "cd74hc163m96.glb",+ "cd74hc163m96.step",+ "cd74hc163m96.lbr",+ "docs/hero.png",+ "docs/cd74hc163m96-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "CD74HC163M96",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Counters, Dividers",+ "datasheet": "https://www.ti.com/cn/lit/gpn/cd74hc161",+ "parts": {+ "symbol": "cd74hc163m96.kicad_sym",+ "footprint": "cd74hc163m96.kicad_mod",+ "model_3d": "cd74hc163m96-etched.glb",+ "model_3d_plain": "cd74hc163m96.glb",+ "model_3d_step": "cd74hc163m96-etched.step",+ "model_3d_step_plain": "cd74hc163m96.step",+ "lbr": "cd74hc163m96.lbr"+ },+ "distributor_links": {+ "lcsc": "C1879801",+ "digikey": "296-CD74HC163M96TR-ND",+ "mouser": "595-CD74HC163M96"+ },+ "distributor_check": {+ "checked_at": "2026-09-26T23:09:43Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-CD74HC163M96TR-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-CD74HC163M96",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "MR",+ "type": "input",+ "description": "Master Reset (active-low synchronous reset for HC163); MR must be low one setup time before the rising clock edge to synchronously clear all outputs to low."+ },+ {+ "number": "2",+ "name": "CP",+ "type": "input",+ "description": "Clock input; counting and parallel loading are accomplished synchronously on the negative-to-positive (low-to-high) transition of CP; maximum frequency 30 MHz (min) at VCC = 4.5 V."+ },+ {+ "number": "3",+ "name": "P0",+ "type": "input",+ "description": "Parallel data input bit 0; loaded into counter on rising CP edge when SPE is low; input unit load 0.25 for HCT types."+ },+ {+ "number": "4",+ "name": "P1",+ "type": "input",+ "description": "Parallel data input bit 1; loaded into counter on rising CP edge when SPE is low; input unit load 0.25 for HCT types."+ },+ {+ "number": "5",+ "name": "P2",+ "type": "input",+ "description": "Parallel data input bit 2; loaded into counter on rising CP edge when SPE is low; input unit load 0.25 for HCT types."+ },+ {+ "number": "6",+ "name": "P3",+ "type": "input",+ "description": "Parallel data input bit 3; loaded into counter on rising CP edge when SPE is low; input unit load 0.25 for HCT types."+ },+ {+ "number": "7",+ "name": "PE",+ "type": "input",+ "description": "Count Enable Parallel input; both PE and TE must be high to enable counting; high-to-low transition of PE should only occur while CP is high; input unit load 0.65 for HCT types."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground supply reference; DC VCC or ground current ICC rated ±50 mA maximum."+ },+ {+ "number": "9",+ "name": "SPE",+ "type": "input",+ "description": "Synchronous Parallel Enable (active-low); when low, disables counting and allows P0-P3 data to be loaded on the next rising CP edge; setup time 12 ns min at VCC = 4.5 V; input unit load 0.5 for HCT types."+ },+ {+ "number": "10",+ "name": "TE",+ "type": "input",+ "description": "Count Enable Trickle input; both PE and TE must be high to count; TE is gated with Q0-Q3 to drive TC high at terminal count; input unit load 1.05 for HCT types."+ },+ {+ "number": "11",+ "name": "Q3",+ "type": "output",+ "description": "Counter output bit 3 (MSB); updated synchronously on rising CP edge; VOH ≥ 3.98 V at IO = −4 mA, VCC = 4.5 V; drives 10 LSTTL loads standard or 15 LSTTL loads bus-driver."+ },+ {+ "number": "12",+ "name": "Q2",+ "type": "output",+ "description": "Counter output bit 2; updated synchronously on rising CP edge; VOH ≥ 3.98 V at IO = −4 mA, VCC = 4.5 V; propagation delay CP-to-Qn 37 ns max at VCC = 4.5 V, 25 °C."+ },+ {+ "number": "13",+ "name": "Q1",+ "type": "output",+ "description": "Counter output bit 1; updated synchronously on rising CP edge; VOL ≤ 0.26 V at IO = 4 mA, VCC = 4.5 V."+ },+ {+ "number": "14",+ "name": "Q0",+ "type": "output",+ "description": "Counter output bit 0 (LSB); updated synchronously on rising CP edge; VOH ≥ 3.98 V at IO = −4 mA, VCC = 4.5 V."+ },+ {+ "number": "15",+ "name": "TC",+ "type": "output",+ "description": "Terminal Count (look-ahead carry) output; goes high for one clock period when TE is high and counter reaches maximum count (HHHH); propagation delay CP-to-TC 37 ns max at VCC = 4.5 V, 25 °C; used to enable next cascaded stage."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage; HC types: 2 V to 6 V operating range; absolute maximum −0.5 V to 7 V; ICC quiescent ≤ 8 µA typical at VCC = 6 V, 25 °C."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 20,+ "cost_usd": 0.3144,+ "at": "2026-09-26T23:09:24"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/cd74hc161",+ "pages": 20,+ "sha256": "cfdc63695252f714",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}