component

CD74HC161E

Public Made by Adom

by adom

Texas Instruments Counters, Dividers, PDIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogiccd74hc161efactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
cd74hc161e / README.md
History Download
Ray Publish 0.1.0 b3adabf 7d ago

CD74HC161E

Texas Instruments · Counters, Dividers · PDIP-16

CD74HC161E from Texas Instruments, in a PDIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MR input Active-low master reset; a low level resets all Q outputs to low asynchronously on the '161, regardless of clock or enable levels.
2 CP input Clock input; counting and parallel presetting occur on the negative-to-positive (low-to-high) clock transition.
3 P0 input Parallel data input bit 0, loaded into the counter on the clock edge when SPE is low, subject to the SPE setup and hold requirements.
4 P1 input Parallel data input bit 1, loaded into the counter on the clock edge when SPE is low, subject to the SPE setup and hold requirements.
5 P2 input Parallel data input bit 2, loaded into the counter on the clock edge when SPE is low, subject to the SPE setup and hold requirements.
6 P3 input Parallel data input bit 3, loaded into the counter on the clock edge when SPE is low, subject to the SPE setup and hold requirements.
7 PE input Count enable (parallel enable); both PE and TE must be high for the counter to count.
8 GND power_in Ground reference pin for the device.
9 SPE input Synchronous parallel enable; a low level disables counting and allows data at P0 to P3 to be loaded on the clock edge, provided SPE setup and hold times are met.
10 TE input Count enable (terminal count enable); gated with the Q outputs so that TC goes high for one clock period at maximum count when TE is high, used for cascading.
11 Q3 output Counter output bit 3 (most significant bit).
12 Q2 output Counter output bit 2.
13 Q1 output Counter output bit 1.
14 Q0 output Counter output bit 0 (least significant bit).
15 TC output Terminal count output; goes high for one clock period when TE is high and the counter is at terminal count (HHHH), enabling the next cascaded stage.
16 VCC power_in Positive supply; HC types operate from 2 V to 6 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage VCC -0.5 7 V 4
DC Input Diode Current IIK -20 20 mA For VI < -0.5V or VI > VCC + 0.5V 4
DC Output Diode Current IOK -20 20 mA For VO < -0.5V or VO > VCC + 0.5V 4
DC Drain Current, per Output IO -25 25 mA For -0.5V < VO < VCC + 0.5V 4
DC Output Source or Sink Current per Output Pin IO -25 25 mA For VO > -0.5V or VO < VCC + 0.5V (as printed) 4
DC VCC or Ground Current ICC -50 50 mA 4
Maximum Storage Temperature Range -65 150 °C 4
Maximum Lead Temperature (Soldering) 300 °C Soldering 10s (SOIC - lead tips only) 4
Maximum Junction Temperature 150 °C 4
Temperature Range TA -55 125 °C 4
Supply Voltage Range, HC Types VCC 2 6 V HC types 4
DC Input or Output Voltage VI, VO 0 V Maximum printed as VCC 4
Input Rise and Fall Time 1000 ns VCC = 2V 4
Input Rise and Fall Time 500 ns VCC = 4.5V 4
Input Rise and Fall Time 400 ns VCC = 6V 4
Thermal Resistance Junction-to-Ambient, E (PDIP) Package θJA 67 °C/W Typical, per JESD 51-7 (Note 4) 4
High Level Input Voltage VIH 1.5 V VCC = 2V; min over -55 to 125°C 4
High Level Input Voltage VIH 3.15 V VCC = 4.5V; min over -55 to 125°C 4
High Level Input Voltage VIH 4.2 V VCC = 6V; min over -55 to 125°C 4
Low Level Input Voltage VIL 0.5 V VCC = 2V; max over -55 to 125°C 4
Low Level Input Voltage VIL 1.35 V VCC = 4.5V; max over -55 to 125°C 4
Low Level Input Voltage VIL 1.8 V VCC = 6V; max over -55 to 125°C 4
High Level Output Voltage, CMOS Loads VOH 1.9 V VI = VIH or VIL, IO = -0.02 mA, VCC = 2V 4
High Level Output Voltage, CMOS Loads VOH 4.4 V VI = VIH or VIL, IO = -0.02 mA, VCC = 4.5V 4
High Level Output Voltage, CMOS Loads VOH 5.9 V VI = VIH or VIL, IO = -0.02 mA, VCC = 6V 4
High Level Output Voltage, TTL Loads VOH 3.7 V IO = -4 mA, VCC = 4.5V; min over -55 to 125°C 4
High Level Output Voltage, TTL Loads VOH 5.2 V IO = -5.2 mA, VCC = 6V; min over -55 to 125°C 4
Low Level Output Voltage, CMOS Loads VOL 0.1 V VI = VIH or VIL, IO = 0.02 mA, VCC = 2V 4
Low Level Output Voltage, TTL Loads VOL 0.4 V IO = 4 mA, VCC = 4.5V; max over -55 to 125°C 4
Input Leakage Current II -1 1 µA VI = VCC or GND, VCC = 6V; over -55 to 125°C 4
Quiescent Device Current ICC 160 µA VI = VCC or GND, IO = 0, VCC = 6V; over -55 to 125°C 4
Propagation Delay CP to TC tPHL, tPLH 280 ns CL = 50pF, VCC = 2V; over -55 to 125°C 6
Propagation Delay CP to TC tPHL, tPLH 56 ns CL = 50pF, VCC = 4.5V; over -55 to 125°C 6
Propagation Delay CP to TC tPHL, tPLH 48 ns CL = 50pF, VCC = 6V; over -55 to 125°C 6
Propagation Delay CP to Qn tPHL, tPLH 280 ns CL = 50pF, VCC = 2V; over -55 to 125°C 6
Propagation Delay CP to Qn tPHL, tPLH 56 ns CL = 50pF, VCC = 4.5V; over -55 to 125°C 6
Propagation Delay CP to Qn tPHL, tPLH 48 ns CL = 50pF, VCC = 6V; over -55 to 125°C 6
Propagation Delay TE to TC tPHL, tPLH 180 ns CL = 50pF, VCC = 2V; over -55 to 125°C 6
Propagation Delay TE to TC tPHL, tPLH 36 ns CL = 50pF, VCC = 4.5V; over -55 to 125°C 6
Propagation Delay TE to TC tPHL, tPLH 31 ns CL = 50pF, VCC = 6V; over -55 to 125°C 6
Propagation Delay MR to Qn (161) tPHL 315 ns CL = 50pF, VCC = 2V; over -55 to 125°C 8
Propagation Delay MR to Qn (161) tPHL 63 ns CL = 50pF, VCC = 4.5V; over -55 to 125°C 8
Propagation Delay MR to Qn (161) tPHL 54 ns CL = 50pF, VCC = 6V; over -55 to 125°C 8
Output Transition Time tTHL, tTLH 110 ns CL = 50pF, VCC = 2V; over -55 to 125°C 8
Output Transition Time tTHL, tTLH 22 ns CL = 50pF, VCC = 4.5V; over -55 to 125°C 8
Output Transition Time tTHL, tTLH 19 ns CL = 50pF, VCC = 6V; over -55 to 125°C 8
Maximum CP Frequency (non-cascaded) fMAX 4 MHz VCC = 2V; min over -55 to 125°C 6
Maximum CP Frequency (non-cascaded) fMAX 20 MHz VCC = 4.5V; min over -55 to 125°C 6
Maximum CP Frequency (non-cascaded) fMAX 24 MHz VCC = 6V; min over -55 to 125°C 6
CP Width (Low) tW(L) 120 ns VCC = 2V; min over -55 to 125°C 6
CP Width (Low) tW(L) 24 ns VCC = 4.5V; min over -55 to 125°C 6
CP Width (Low) tW(L) 20 ns VCC = 6V; min over -55 to 125°C 6
Setup Time, Pn to CP tSU 90 ns VCC = 2V; min over -55 to 125°C 6
Setup Time, Pn to CP tSU 18 ns VCC = 4.5V; min over -55 to 125°C 6
Setup Time, Pn to CP tSU 15 ns VCC = 6V; min over -55 to 125°C 6

CAD (KiCad official)

  • Symbol: CD74HC161E
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: PDIP-16 (KiCad packages3D, STEP)
  • 3D model files: cd74hc161e-etched.step / cd74hc161e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hc161e.step / cd74hc161e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (20 pp, sha256 cfdc63695252f714, retrieved 2026-10-16, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF