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CD74HC154M96

Public Made by Adom

by adom

Texas Instruments Signal Switches / Encoders & Decoders / Multiplexers, SOIC-24-300mil. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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docs cd74hc154m96: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers cd74hc154m96: viewers · Ray
cd74hc154m96-etched.fit.json cd74hc154m96: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd74hc154m96-etched.glb cd74hc154m96: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd74hc154m96-etched.step cd74hc154m96: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd74hc154m96.glb Publish 0.1.0 · Ray
cd74hc154m96.kicad_mod Publish 0.1.0 · Ray
cd74hc154m96.kicad_sym Publish 0.1.0 · Ray
cd74hc154m96.lbr Publish 0.1.0 · Ray
cd74hc154m96.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json cd74hc154m96: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md cd74hc154m96: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray

CD74HC154M96

Texas Instruments · Signal Switches / Encoders & Decoders / Multiplexers · SOIC-24-300mil

CD74HC154M96 from Texas Instruments, in a SOIC-24-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Y0 output Decoded active-LOW output 0. Asserts LOW when address inputs A3:A0 = 0000 and both enables are LOW; HIGH otherwise.
2 Y1 output Decoded active-LOW output 1. Asserts LOW when A3:A0 = 0001 and both enables are LOW.
3 Y2 output Decoded active-LOW output 2. Asserts LOW when A3:A0 = 0010 and both enables are LOW.
4 Y3 output Decoded active-LOW output 3. Asserts LOW when A3:A0 = 0011 and both enables are LOW.
5 Y4 output Decoded active-LOW output 4. Asserts LOW when A3:A0 = 0100 and both enables are LOW.
6 Y5 output Decoded active-LOW output 5. Asserts LOW when A3:A0 = 0101 and both enables are LOW.
7 Y6 output Decoded active-LOW output 6. Asserts LOW when A3:A0 = 0110 and both enables are LOW.
8 Y7 output Decoded active-LOW output 7. Asserts LOW when A3:A0 = 0111 and both enables are LOW.
9 Y8 output Decoded active-LOW output 8. Asserts LOW when A3:A0 = 1000 and both enables are LOW.
10 Y9 output Decoded active-LOW output 9. Asserts LOW when A3:A0 = 1001 and both enables are LOW.
11 Y10 output Decoded active-LOW output 10. Asserts LOW when A3:A0 = 1010 and both enables are LOW.
12 GND power_in Ground reference (0 V). Supply return for all internal logic.
13 Y11 output Decoded active-LOW output 11. Asserts LOW when A3:A0 = 1011 and both enables are LOW.
14 Y12 output Decoded active-LOW output 12. Asserts LOW when A3:A0 = 1100 and both enables are LOW.
15 Y13 output Decoded active-LOW output 13. Asserts LOW when A3:A0 = 1101 and both enables are LOW.
16 Y14 output Decoded active-LOW output 14. Asserts LOW when A3:A0 = 1110 and both enables are LOW.
17 Y15 output Decoded active-LOW output 15. Asserts LOW when A3:A0 = 1111 and both enables are LOW.
18 E2 input Active-LOW enable input 2. Both E1 and E2 must be LOW to enable the decoder; otherwise all Y outputs are forced HIGH.
19 E1 input Active-LOW enable input 1. Both E1 and E2 must be LOW to enable the decoder; otherwise all Y outputs are forced HIGH.
20 A3 input Binary address input bit 3 (MSB). CMOS-level logic input selecting one of the sixteen Y outputs when the device is enabled.
21 A2 input Binary address input bit 2. CMOS-level logic input selecting one of the sixteen Y outputs when the device is enabled.
22 A1 input Binary address input bit 1. CMOS-level logic input selecting one of the sixteen Y outputs when the device is enabled.
23 A0 input Binary address input bit 0 (LSB). CMOS-level logic input selecting one of the sixteen Y outputs when the device is enabled.
24 VCC power_in Positive supply voltage input, 2 V to 6 V operating range. Bypass locally with a 0.1 uF ceramic capacitor to GND.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-24-300mil
Category Logic
Pins 24

Ordering variants

Same part, different packaging or reel option.

  • CD74HC154M96
  • CD74HC154M96M
  • CD74HC154M96MT
  • CD74HC154M96E
  • CD74HC154M96EN
  • CD74HC154M96NSR
  • CD74HC154M96PW
  • CD74HC154M96PWR

CAD (KiCad official)

  • Symbol: CD74HC154M96
  • Footprint: Package_SO:SOIC-24W_7.5x15.4mm_P1.27mm
  • 3D model: SOIC-24-300mil (KiCad packages3D, STEP)
  • 3D model files: cd74hc154m96-etched.step / cd74hc154m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hc154m96.step / cd74hc154m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (15 pp, sha256 e9dd64aa8bcfe428, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF