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CD74HC123PW

Public Made by Adom

by adom

Texas Instruments Monostable Multivibrators, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic icscd74hc123pwfactory-2.0.0extractor-text

Verified CD74HC123PW

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CD74HC123PW · TSSOP-16 · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 24-page datasheet
  • ✓distributor: lcsc C2862972, digikey 296-25971-5-ND, mouser 595-CD74HC123PW
  • ✓family: TSSOP-16_4.4x5mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-uebgj6n9/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.20)
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cd74hc123pw.kicad_sym✓ cd74hc123pw.kicad_mod✓ cd74hc123pw.step
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Contents

README

markdown

CD74HC123PW

Texas Instruments · Monostable Multivibrators · TSSOP-16

CD74HC123PW from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Monostable 1 trigger input A (Schmitt trigger) for trailing-edge triggering.
2 1B input Monostable 1 trigger input B (Schmitt trigger) for leading-edge triggering.
3 1R input Monostable 1 reset input; a LOW level terminates the output pulse.
4 1Q̄ output Monostable 1 buffered complementary output Q-bar.
5 2Q output Monostable 2 buffered output Q.
6 2CX passive Monostable 2 external timing capacitor connection (CX minimum is 0pF).
7 2RXCX passive Monostable 2 external timing resistor/capacitor junction (RX typically 5kΩ minimum; tW = 0.45 RX CX at VCC = 5V).
8 GND power_in Ground.
9 2A input Monostable 2 trigger input A (Schmitt trigger) for trailing-edge triggering.
10 2B input Monostable 2 trigger input B (Schmitt trigger) for leading-edge triggering.
11 2R input Monostable 2 reset input; a LOW level terminates the output pulse.
12 2Q̄ output Monostable 2 buffered complementary output Q-bar.
13 1Q output Monostable 1 buffered output Q.
14 1CX passive Monostable 1 external timing capacitor connection (CX minimum is 0pF).
15 1RXCX passive Monostable 1 external timing resistor/capacitor junction (RX typically 5kΩ minimum; tW = 0.45 RX CX at VCC = 5V).
16 VCC power_in Positive supply voltage, 2V to 6V for HC types.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category Logic ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High Level Input Voltage (HC) VIH 1.5 V VCC=2 V, TA=-55 to 125°C 3
High Level Input Voltage (HC) VIH 3.15 V VCC=4.5 V, TA=-55 to 125°C 3
High Level Input Voltage (HC) VIH 4.2 V VCC=6 V, TA=-55 to 125°C 3
Low Level Input Voltage (HC) VIL 0.5 V VCC=2 V, TA=-55 to 125°C 3
Low Level Input Voltage (HC) VIL 1.35 V VCC=4.5 V, TA=-55 to 125°C 3
Low Level Input Voltage (HC) VIL 1.8 V VCC=6 V, TA=-55 to 125°C 3
High Level Output Voltage, CMOS Loads VOH 1.9 V VI=VIH or VIL, IO=-0.02 mA, VCC=2 V, TA=-55 to 125°C 3
High Level Output Voltage, CMOS Loads VOH 4.4 V VI=VIH or VIL, IO=-0.02 mA, VCC=4.5 V, TA=-55 to 125°C 3
High Level Output Voltage, CMOS Loads VOH 5.9 V VI=VIH or VIL, IO=-0.02 mA, VCC=6 V, TA=-55 to 125°C 3
High Level Output Voltage, TTL Loads VOH 3.7 V VI=VIH or VIL, IO=-4 mA, VCC=4.5 V, TA=-55 to 125°C 3
High Level Output Voltage, TTL Loads VOH 5.2 V VI=VIH or VIL, IO=-5.2 mA, VCC=6 V, TA=-55 to 125°C 3
Low Level Output Voltage, CMOS Loads VOL 0.1 V VI=VIH or VIL, IO=0.02 mA, VCC=2 V, TA=-55 to 125°C 3
Low Level Output Voltage, TTL Loads VOL 0.4 V VI=VIH or VIL, IO=4 mA, VCC=4.5 V, TA=-55 to 125°C 3
Input Leakage Current II -1 1 µA VI=VCC or GND, VCC=6 V, TA=-55 to 125°C 3
Quiescent Device Current ICC 160 µA VI=VCC or GND, IO=0, VCC=6 V, TA=-55 to 125°C 3
Minimum Input Pulse Width, A tWL 150 ns VCC=2 V, TA=-55 to 125°C 4
Minimum Input Pulse Width, A tWL 30 ns VCC=4.5 V, TA=-55 to 125°C 4
Minimum Input Pulse Width, A tWL 26 ns VCC=6 V, TA=-55 to 125°C 4
Minimum Input Pulse Width, B tWH 150 ns VCC=2 V, TA=-55 to 125°C 4
Minimum Input Pulse Width, B tWH 30 ns VCC=4.5 V, TA=-55 to 125°C 4
Minimum Input Pulse Width, B tWH 26 ns VCC=6 V, TA=-55 to 125°C 4
Minimum Input Pulse Width, R tWL 150 150 ns VCC=2 V, TA=-55 to 125°C 5
Minimum Input Pulse Width, R tWL 30 30 ns VCC=4.5 V, TA=-55 to 125°C 5
Minimum Input Pulse Width, R tWL 26 26 ns VCC=6 V, TA=-55 to 125°C 5
A and B Hold Time tH 75 75 ns VCC=2 V, TA=-55 to 125°C 5
A and B Hold Time tH 15 15 ns VCC=4.5 V, TA=-55 to 125°C 5
A and B Hold Time tH 13 13 ns VCC=6 V, TA=-55 to 125°C 5
Reset Removal Time tREM 75 75 ns VCC=2 V, TA=-55 to 125°C 5
Reset Removal Time tREM 15 15 ns VCC=4.5 V, TA=-55 to 125°C 5
Reset Removal Time tREM 13 13 ns VCC=6 V, TA=-55 to 125°C 5
Output Pulse Width, Q or Q̄ tW 38.2 51.8 µs VCC=5 V, RX=10kΩ, CX=10nF, TA=-55 to 125°C 5
Trigger Propagation Delay, A, B, R to Q tPLH 450 ns CL=50 pF, VCC=2 V, input tr,tf=6 ns, RX=10kΩ, CX=0, TA=-55 to 125°C 6
Trigger Propagation Delay, A, B, R to Q tPLH 90 ns CL=50 pF, VCC=4.5 V, input tr,tf=6 ns, RX=10kΩ, CX=0, TA=-55 to 125°C 6
Trigger Propagation Delay, A, B, R to Q tPLH 76 ns CL=50 pF, VCC=6 V, input tr,tf=6 ns, RX=10kΩ, CX=0, TA=-55 to 125°C 6
Trigger Propagation Delay, A, B, R to Q tPHL 480 ns CL=50 pF, VCC=2 V, input tr,tf=6 ns, RX=10kΩ, CX=0, TA=-55 to 125°C 6
Trigger Propagation Delay, A, B, R to Q tPHL 96 ns CL=50 pF, VCC=4.5 V, input tr,tf=6 ns, RX=10kΩ, CX=0, TA=-55 to 125°C 6
Trigger Propagation Delay, A, B, R to Q tPHL 82 ns CL=50 pF, VCC=6 V, input tr,tf=6 ns, RX=10kΩ, CX=0, TA=-55 to 125°C 6
Reset Propagation Delay, R to Q or Q̄ tPHL,tPLH 325 ns CL=50 pF, VCC=2 V, input tr,tf=6 ns, RX=10kΩ, CX=0, TA=-55 to 125°C 6
Reset Propagation Delay, R to Q or Q̄ tPHL,tPLH 65 ns CL=50 pF, VCC=4.5 V, input tr,tf=6 ns, RX=10kΩ, CX=0, TA=-55 to 125°C 6
Reset Propagation Delay, R to Q or Q̄ tPHL,tPLH 55 ns CL=50 pF, VCC=6 V, input tr,tf=6 ns, RX=10kΩ, CX=0, TA=-55 to 125°C 6
Output Transition Time tTHL,tTLH 110 ns CL=50 pF, VCC=2 V, input tr,tf=6 ns, RX=10kΩ, CX=0, TA=-55 to 125°C 6
Output Transition Time tTHL,tTLH 22 ns CL=50 pF, VCC=4.5 V, input tr,tf=6 ns, RX=10kΩ, CX=0, TA=-55 to 125°C 6
Output Transition Time tTHL,tTLH 19 ns CL=50 pF, VCC=6 V, input tr,tf=6 ns, RX=10kΩ, CX=0, TA=-55 to 125°C 6
Pulse Width Match Between Circuits in the Same Package -2 2 % RX=10kΩ, CX=10pF, VCC=5 V 6
Recommended Supply Voltage Range (HC types) VCC 2 6 V HC types 3
Operating Temperature Range TA -55 125 °C 3
Input Rise and Fall Time 1000 ns VCC=2 V 3
Input Rise and Fall Time 500 ns VCC=4.5 V 3
Input Rise and Fall Time 400 ns VCC=6 V 3
DC Supply Voltage VCC -0.5 7 V 3
DC Input Diode Current IIK -20 20 mA For VI < -0.5 V or VI > VCC + 0.5 V 3
DC Output Diode Current IOK -20 20 mA For VO < -0.5 V or VO > VCC + 0.5 V 3
DC Output Source or Sink Current per Output Pin IO -25 25 mA For VO > -0.5 V or VO < VCC + 0.5 V 3
DC VCC or Ground Current ICC or IGND -50 50 mA 3
Maximum Junction Temperature 150 °C 3
Maximum Storage Temperature Range -65 150 °C 3
Package Thermal Impedance, PW (TSSOP) Package θJA 108 °C/W Per JESD 51-7 3

CAD (KiCad official)

  • Symbol: CD74HC123PW
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: cd74hc123pw-etched.step / cd74hc123pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hc123pw.step / cd74hc123pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (24 pp, sha256 062aa4848f2f6eae, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF