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CD74HC112M96
Public Made by Adomby adom
Texas Instruments Flip Flops, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+53@@ -0,0 +1,53 @@+# CD74HC112M96++**Texas Instruments** · Flip Flops · SOIC-16++CD74HC112M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1CLK | input | Clock input for flip-flop 1; negative-edge triggered with input hysteresis; fMAX 30 MHz typ at VCC=4.5 V, 60 MHz typ at VCC=5 V (CL=15 pF); minimum pulse width 16 ns (VCC=4.5 V). |+| 2 | 1K | input | K data input for flip-flop 1; buffered CMOS input; setup time 16 ns min, hold time 0 ns (VCC=4.5 V); VIH ≥ 3.15 V, VIL ≤ 1.35 V at VCC=4.5 V (HC type). |+| 3 | 1J | input | J data input for flip-flop 1; buffered CMOS input; setup time 16 ns min, hold time 0 ns (VCC=4.5 V); VIH ≥ 3.15 V, VIL ≤ 1.35 V at VCC=4.5 V (HC type). |+| 4 | 1PRE | input | Active-low asynchronous preset input for flip-flop 1; forces 1Q high independent of clock; minimum pulse width 16 ns (VCC=4.5 V); removal time to CLK 16 ns min. |+| 5 | 1Q | output | True output of flip-flop 1; VOH ≥ 3.98 V at IOH=−4 mA, VOL ≤ 0.33 V at IOL=4 mA (VCC=4.5 V, 25°C); propagation delay from CLK 35 ns max (VCC=4.5 V). |+| 6 | 1Q_N | output | Complement output of flip-flop 1; VOH ≥ 3.98 V at IOH=−4 mA, VOL ≤ 0.33 V at IOL=4 mA (VCC=4.5 V, 25°C); propagation delay from CLK 35 ns max (VCC=4.5 V). |+| 7 | 2Q_N | output | Complement output of flip-flop 2; VOH ≥ 3.98 V at IOH=−4 mA, VOL ≤ 0.33 V at IOL=4 mA (VCC=4.5 V, 25°C); propagation delay from 2CLK 35 ns max (VCC=4.5 V). |+| 8 | GND | power_in | Ground reference; continuous current through GND pin ±50 mA absolute maximum. |+| 9 | 2Q | output | True output of flip-flop 2; VOH ≥ 3.98 V at IOH=−4 mA, VOL ≤ 0.33 V at IOL=4 mA (VCC=4.5 V, 25°C); propagation delay from 2CLK 35 ns max (VCC=4.5 V). |+| 10 | 2PRE | input | Active-low asynchronous preset input for flip-flop 2; forces 2Q high independent of clock; minimum pulse width 16 ns (VCC=4.5 V); removal time to 2CLK 16 ns min. |+| 11 | 2J | input | J data input for flip-flop 2; buffered CMOS input; setup time 16 ns min, hold time 0 ns (VCC=4.5 V); VIH ≥ 3.15 V, VIL ≤ 1.35 V at VCC=4.5 V (HC type). |+| 12 | 2K | input | K data input for flip-flop 2; buffered CMOS input; setup time 16 ns min, hold time 0 ns (VCC=4.5 V); VIH ≥ 3.15 V, VIL ≤ 1.35 V at VCC=4.5 V (HC type). |+| 13 | 2CLK | input | Clock input for flip-flop 2; negative-edge triggered with input hysteresis; fMAX 30 MHz typ at VCC=4.5 V, 60 MHz typ at VCC=5 V (CL=15 pF); minimum pulse width 16 ns (VCC=4.5 V). |+| 14 | 2CLR | input | Active-low asynchronous clear input for flip-flop 2; forces 2Q low independent of clock; minimum pulse width 16 ns (VCC=4.5 V); removal time to 2CLK 16 ns min. |+| 15 | 1CLR | input | Active-low asynchronous clear input for flip-flop 1; forces 1Q low independent of clock; minimum pulse width 16 ns (VCC=4.5 V); removal time to 1CLK 16 ns min. |+| 16 | VCC | power_in | Positive supply voltage; HC types 2 V to 6 V, HCT types 4.5 V to 5.5 V; absolute maximum 7 V; continuous current ±50 mA absolute maximum. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `CD74HC112M96`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)+- 3D model files: `cd74hc112m96-etched.step` / `cd74hc112m96-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74hc112m96.step` / `cd74hc112m96.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd74hct112) (27 pp, sha256 `378985f635dcc264`, retrieved 2026-09-26, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-sonnet-4-6` (text+vision), consensus `claude-opus-4-7` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd74hc112m96-datasheet.pdf)
page.jsonadded+206@@ -0,0 +1,206 @@+{+ "slug": "cd74hc112m96",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Flip Flops, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "cd74hc112m96",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cd74hc112m96.kicad_sym",+ "cd74hc112m96.kicad_mod",+ "cd74hc112m96.glb",+ "cd74hc112m96.step",+ "cd74hc112m96.lbr",+ "docs/hero.png",+ "docs/cd74hc112m96-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "CD74HC112M96",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Flip Flops",+ "datasheet": "https://www.ti.com/cn/lit/gpn/cd74hct112",+ "parts": {+ "symbol": "cd74hc112m96.kicad_sym",+ "footprint": "cd74hc112m96.kicad_mod",+ "model_3d": "cd74hc112m96-etched.glb",+ "model_3d_plain": "cd74hc112m96.glb",+ "model_3d_step": "cd74hc112m96-etched.step",+ "model_3d_step_plain": "cd74hc112m96.step",+ "lbr": "cd74hc112m96.lbr"+ },+ "distributor_links": {+ "lcsc": "C2878059",+ "digikey": "296-12777-2-ND",+ "mouser": "595-CD74HC112M96"+ },+ "distributor_check": {+ "checked_at": "2026-09-26T13:20:20Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-12777-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-CD74HC112M96",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "1CLK",+ "type": "input",+ "description": "Clock input for flip-flop 1; negative-edge triggered with input hysteresis; fMAX 30 MHz typ at VCC=4.5 V, 60 MHz typ at VCC=5 V (CL=15 pF); minimum pulse width 16 ns (VCC=4.5 V)."+ },+ {+ "number": "2",+ "name": "1K",+ "type": "input",+ "description": "K data input for flip-flop 1; buffered CMOS input; setup time 16 ns min, hold time 0 ns (VCC=4.5 V); VIH ≥ 3.15 V, VIL ≤ 1.35 V at VCC=4.5 V (HC type)."+ },+ {+ "number": "3",+ "name": "1J",+ "type": "input",+ "description": "J data input for flip-flop 1; buffered CMOS input; setup time 16 ns min, hold time 0 ns (VCC=4.5 V); VIH ≥ 3.15 V, VIL ≤ 1.35 V at VCC=4.5 V (HC type)."+ },+ {+ "number": "4",+ "name": "1PRE",+ "type": "input",+ "description": "Active-low asynchronous preset input for flip-flop 1; forces 1Q high independent of clock; minimum pulse width 16 ns (VCC=4.5 V); removal time to CLK 16 ns min."+ },+ {+ "number": "5",+ "name": "1Q",+ "type": "output",+ "description": "True output of flip-flop 1; VOH ≥ 3.98 V at IOH=−4 mA, VOL ≤ 0.33 V at IOL=4 mA (VCC=4.5 V, 25°C); propagation delay from CLK 35 ns max (VCC=4.5 V)."+ },+ {+ "number": "6",+ "name": "1Q_N",+ "type": "output",+ "description": "Complement output of flip-flop 1; VOH ≥ 3.98 V at IOH=−4 mA, VOL ≤ 0.33 V at IOL=4 mA (VCC=4.5 V, 25°C); propagation delay from CLK 35 ns max (VCC=4.5 V)."+ },+ {+ "number": "7",+ "name": "2Q_N",+ "type": "output",+ "description": "Complement output of flip-flop 2; VOH ≥ 3.98 V at IOH=−4 mA, VOL ≤ 0.33 V at IOL=4 mA (VCC=4.5 V, 25°C); propagation delay from 2CLK 35 ns max (VCC=4.5 V)."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference; continuous current through GND pin ±50 mA absolute maximum."+ },+ {+ "number": "9",+ "name": "2Q",+ "type": "output",+ "description": "True output of flip-flop 2; VOH ≥ 3.98 V at IOH=−4 mA, VOL ≤ 0.33 V at IOL=4 mA (VCC=4.5 V, 25°C); propagation delay from 2CLK 35 ns max (VCC=4.5 V)."+ },+ {+ "number": "10",+ "name": "2PRE",+ "type": "input",+ "description": "Active-low asynchronous preset input for flip-flop 2; forces 2Q high independent of clock; minimum pulse width 16 ns (VCC=4.5 V); removal time to 2CLK 16 ns min."+ },+ {+ "number": "11",+ "name": "2J",+ "type": "input",+ "description": "J data input for flip-flop 2; buffered CMOS input; setup time 16 ns min, hold time 0 ns (VCC=4.5 V); VIH ≥ 3.15 V, VIL ≤ 1.35 V at VCC=4.5 V (HC type)."+ },+ {+ "number": "12",+ "name": "2K",+ "type": "input",+ "description": "K data input for flip-flop 2; buffered CMOS input; setup time 16 ns min, hold time 0 ns (VCC=4.5 V); VIH ≥ 3.15 V, VIL ≤ 1.35 V at VCC=4.5 V (HC type)."+ },+ {+ "number": "13",+ "name": "2CLK",+ "type": "input",+ "description": "Clock input for flip-flop 2; negative-edge triggered with input hysteresis; fMAX 30 MHz typ at VCC=4.5 V, 60 MHz typ at VCC=5 V (CL=15 pF); minimum pulse width 16 ns (VCC=4.5 V)."+ },+ {+ "number": "14",+ "name": "2CLR",+ "type": "input",+ "description": "Active-low asynchronous clear input for flip-flop 2; forces 2Q low independent of clock; minimum pulse width 16 ns (VCC=4.5 V); removal time to 2CLK 16 ns min."+ },+ {+ "number": "15",+ "name": "1CLR",+ "type": "input",+ "description": "Active-low asynchronous clear input for flip-flop 1; forces 1Q low independent of clock; minimum pulse width 16 ns (VCC=4.5 V); removal time to 1CLK 16 ns min."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage; HC types 2 V to 6 V, HCT types 4.5 V to 5.5 V; absolute maximum 7 V; continuous current ±50 mA absolute maximum."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-sonnet-4-6",+ "primary_mode": "text+vision",+ "consensus_model": "claude-opus-4-7",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "vision extraction: provenance cannot be text-verified; needs consensus"+ ],+ "pages_sent": 27,+ "cost_usd": 0.6239,+ "at": "2026-09-26T13:20:03"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/cd74hct112",+ "pages": 27,+ "sha256": "378985f635dcc264",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}