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CD74HC109M96
Public Made by Adomby adom
Texas Instruments Flip Flops, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# CD74HC109M96++**Texas Instruments** · Flip Flops · SOIC-16++CD74HC109M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | ~{1R} | input | Active-low asynchronous reset input for flip-flop 1; driving low forces 1Q low and ~{1Q} high regardless of clock state; tREM = 16 ns min at VCC = 4.5 V. |+| 2 | 1J | input | J data input for flip-flop 1; sampled on positive edge of 1CP; tSU = 16 ns min, tH = 5 ns min at VCC = 4.5 V. |+| 3 | ~{1K} | input | Active-low K input (K̄) for flip-flop 1; per truth table a low level is treated as K=H (enabling toggle or reset); tSU = 16 ns min at VCC = 4.5 V. |+| 4 | 1CP | input | Schmitt-trigger positive-edge clock input for flip-flop 1; fMAX = 30 MHz typ at VCC = 4.5 V, CL = 50 pF; minimum pulse width tW = 16 ns at VCC = 4.5 V. |+| 5 | ~{1S} | input | Active-low asynchronous set input for flip-flop 1; driving low forces 1Q high and ~{1Q} low regardless of clock state; tPLH to Q ≤ 24 ns max at VCC = 4.5 V. |+| 6 | 1Q | output | True Q output for flip-flop 1; VOH ≥ 4.4 V at VCC = 4.5 V with IO = −0.02 mA; tPHL from CP ≤ 44 ns max at VCC = 4.5 V. |+| 7 | ~{1Q} | output | Complement Q output for flip-flop 1; VOL ≤ 0.1 V at VCC = 4.5 V with IO = 0.02 mA; transitions complement to 1Q. |+| 8 | GND | power_in | Ground supply reference; maximum ICC = ±50 mA; 0 V reference for all logic levels. |+| 9 | ~{2Q} | output | Complement Q output for flip-flop 2; VOL ≤ 0.1 V at VCC = 4.5 V with IO = 0.02 mA; transitions complement to 2Q. |+| 10 | 2Q | output | True Q output for flip-flop 2; VOH ≥ 4.4 V at VCC = 4.5 V with IO = −0.02 mA; tPHL from 2CP ≤ 44 ns max at VCC = 4.5 V. |+| 11 | ~{2S} | input | Active-low asynchronous set input for flip-flop 2; driving low forces 2Q high and ~{2Q} low regardless of clock state; tREM = 16 ns min at VCC = 4.5 V. |+| 12 | 2CP | input | Schmitt-trigger positive-edge clock input for flip-flop 2; fMAX = 30 MHz typ at VCC = 4.5 V; minimum pulse width tW = 16 ns at VCC = 4.5 V. |+| 13 | ~{2K} | input | Active-low K input (K̄) for flip-flop 2; per truth table a low level is treated as K=H; tSU = 16 ns min at VCC = 4.5 V. |+| 14 | 2J | input | J data input for flip-flop 2; sampled on positive edge of 2CP; tSU = 16 ns min, tH = 5 ns min at VCC = 4.5 V. |+| 15 | ~{2R} | input | Active-low asynchronous reset input for flip-flop 2; driving low forces 2Q low and ~{2Q} high regardless of clock state; tPHL to Q ≤ 46 ns max at VCC = 4.5 V. |+| 16 | VCC | power_in | Positive supply voltage; 2 V to 6 V (HC type) or 4.5 V to 5.5 V (HCT type); quiescent ICC ≤ 40 µA at VCC = 6 V, 85 °C. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `CD74HC109M96`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)+- 3D model files: `cd74hc109m96-etched.step` / `cd74hc109m96-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74hc109m96.step` / `cd74hc109m96.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd74hct109) (16 pp, sha256 `3a88583aff8d86ad`, retrieved 2026-09-27, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd74hc109m96-datasheet.pdf)
page.jsonadded+204@@ -0,0 +1,204 @@+{+ "slug": "cd74hc109m96",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Flip Flops, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "cd74hc109m96",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cd74hc109m96.kicad_sym",+ "cd74hc109m96.kicad_mod",+ "cd74hc109m96.glb",+ "cd74hc109m96.step",+ "cd74hc109m96.lbr",+ "docs/hero.png",+ "docs/cd74hc109m96-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "CD74HC109M96",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Flip Flops",+ "datasheet": "https://www.ti.com/cn/lit/gpn/cd74hct109",+ "parts": {+ "symbol": "cd74hc109m96.kicad_sym",+ "footprint": "cd74hc109m96.kicad_mod",+ "model_3d": "cd74hc109m96-etched.glb",+ "model_3d_plain": "cd74hc109m96.glb",+ "model_3d_step": "cd74hc109m96-etched.step",+ "model_3d_step_plain": "cd74hc109m96.step",+ "lbr": "cd74hc109m96.lbr"+ },+ "distributor_links": {+ "lcsc": "C2677829",+ "digikey": "296-31563-2-ND",+ "mouser": "595-CD74HC109M96"+ },+ "distributor_check": {+ "checked_at": "2026-09-27T03:13:37Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-31563-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-CD74HC109M96",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "~{1R}",+ "type": "input",+ "description": "Active-low asynchronous reset input for flip-flop 1; driving low forces 1Q low and ~{1Q} high regardless of clock state; tREM = 16 ns min at VCC = 4.5 V."+ },+ {+ "number": "2",+ "name": "1J",+ "type": "input",+ "description": "J data input for flip-flop 1; sampled on positive edge of 1CP; tSU = 16 ns min, tH = 5 ns min at VCC = 4.5 V."+ },+ {+ "number": "3",+ "name": "~{1K}",+ "type": "input",+ "description": "Active-low K input (K̄) for flip-flop 1; per truth table a low level is treated as K=H (enabling toggle or reset); tSU = 16 ns min at VCC = 4.5 V."+ },+ {+ "number": "4",+ "name": "1CP",+ "type": "input",+ "description": "Schmitt-trigger positive-edge clock input for flip-flop 1; fMAX = 30 MHz typ at VCC = 4.5 V, CL = 50 pF; minimum pulse width tW = 16 ns at VCC = 4.5 V."+ },+ {+ "number": "5",+ "name": "~{1S}",+ "type": "input",+ "description": "Active-low asynchronous set input for flip-flop 1; driving low forces 1Q high and ~{1Q} low regardless of clock state; tPLH to Q ≤ 24 ns max at VCC = 4.5 V."+ },+ {+ "number": "6",+ "name": "1Q",+ "type": "output",+ "description": "True Q output for flip-flop 1; VOH ≥ 4.4 V at VCC = 4.5 V with IO = −0.02 mA; tPHL from CP ≤ 44 ns max at VCC = 4.5 V."+ },+ {+ "number": "7",+ "name": "~{1Q}",+ "type": "output",+ "description": "Complement Q output for flip-flop 1; VOL ≤ 0.1 V at VCC = 4.5 V with IO = 0.02 mA; transitions complement to 1Q."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground supply reference; maximum ICC = ±50 mA; 0 V reference for all logic levels."+ },+ {+ "number": "9",+ "name": "~{2Q}",+ "type": "output",+ "description": "Complement Q output for flip-flop 2; VOL ≤ 0.1 V at VCC = 4.5 V with IO = 0.02 mA; transitions complement to 2Q."+ },+ {+ "number": "10",+ "name": "2Q",+ "type": "output",+ "description": "True Q output for flip-flop 2; VOH ≥ 4.4 V at VCC = 4.5 V with IO = −0.02 mA; tPHL from 2CP ≤ 44 ns max at VCC = 4.5 V."+ },+ {+ "number": "11",+ "name": "~{2S}",+ "type": "input",+ "description": "Active-low asynchronous set input for flip-flop 2; driving low forces 2Q high and ~{2Q} low regardless of clock state; tREM = 16 ns min at VCC = 4.5 V."+ },+ {+ "number": "12",+ "name": "2CP",+ "type": "input",+ "description": "Schmitt-trigger positive-edge clock input for flip-flop 2; fMAX = 30 MHz typ at VCC = 4.5 V; minimum pulse width tW = 16 ns at VCC = 4.5 V."+ },+ {+ "number": "13",+ "name": "~{2K}",+ "type": "input",+ "description": "Active-low K input (K̄) for flip-flop 2; per truth table a low level is treated as K=H; tSU = 16 ns min at VCC = 4.5 V."+ },+ {+ "number": "14",+ "name": "2J",+ "type": "input",+ "description": "J data input for flip-flop 2; sampled on positive edge of 2CP; tSU = 16 ns min, tH = 5 ns min at VCC = 4.5 V."+ },+ {+ "number": "15",+ "name": "~{2R}",+ "type": "input",+ "description": "Active-low asynchronous reset input for flip-flop 2; driving low forces 2Q low and ~{2Q} high regardless of clock state; tPHL to Q ≤ 46 ns max at VCC = 4.5 V."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage; 2 V to 6 V (HC type) or 4.5 V to 5.5 V (HCT type); quiescent ICC ≤ 40 µA at VCC = 6 V, 85 °C."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 16,+ "cost_usd": 0.2764,+ "at": "2026-09-27T03:13:18"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/cd74hct109",+ "pages": 16,+ "sha256": "3a88583aff8d86ad",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}