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CD74HC109M96

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Texas Instruments Flip Flops, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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CD74HC109M96

Texas Instruments · Flip Flops · SOIC-16

CD74HC109M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 ~{1R} input Active-low asynchronous reset input for flip-flop 1; driving low forces 1Q low and ~{1Q} high regardless of clock state; tREM = 16 ns min at VCC = 4.5 V.
2 1J input J data input for flip-flop 1; sampled on positive edge of 1CP; tSU = 16 ns min, tH = 5 ns min at VCC = 4.5 V.
3 ~{1K} input Active-low K input (K̄) for flip-flop 1; per truth table a low level is treated as K=H (enabling toggle or reset); tSU = 16 ns min at VCC = 4.5 V.
4 1CP input Schmitt-trigger positive-edge clock input for flip-flop 1; fMAX = 30 MHz typ at VCC = 4.5 V, CL = 50 pF; minimum pulse width tW = 16 ns at VCC = 4.5 V.
5 ~{1S} input Active-low asynchronous set input for flip-flop 1; driving low forces 1Q high and ~{1Q} low regardless of clock state; tPLH to Q ≤ 24 ns max at VCC = 4.5 V.
6 1Q output True Q output for flip-flop 1; VOH ≥ 4.4 V at VCC = 4.5 V with IO = −0.02 mA; tPHL from CP ≤ 44 ns max at VCC = 4.5 V.
7 ~{1Q} output Complement Q output for flip-flop 1; VOL ≤ 0.1 V at VCC = 4.5 V with IO = 0.02 mA; transitions complement to 1Q.
8 GND power_in Ground supply reference; maximum ICC = ±50 mA; 0 V reference for all logic levels.
9 ~{2Q} output Complement Q output for flip-flop 2; VOL ≤ 0.1 V at VCC = 4.5 V with IO = 0.02 mA; transitions complement to 2Q.
10 2Q output True Q output for flip-flop 2; VOH ≥ 4.4 V at VCC = 4.5 V with IO = −0.02 mA; tPHL from 2CP ≤ 44 ns max at VCC = 4.5 V.
11 ~{2S} input Active-low asynchronous set input for flip-flop 2; driving low forces 2Q high and ~{2Q} low regardless of clock state; tREM = 16 ns min at VCC = 4.5 V.
12 2CP input Schmitt-trigger positive-edge clock input for flip-flop 2; fMAX = 30 MHz typ at VCC = 4.5 V; minimum pulse width tW = 16 ns at VCC = 4.5 V.
13 ~{2K} input Active-low K input (K̄) for flip-flop 2; per truth table a low level is treated as K=H; tSU = 16 ns min at VCC = 4.5 V.
14 2J input J data input for flip-flop 2; sampled on positive edge of 2CP; tSU = 16 ns min, tH = 5 ns min at VCC = 4.5 V.
15 ~{2R} input Active-low asynchronous reset input for flip-flop 2; driving low forces 2Q low and ~{2Q} high regardless of clock state; tPHL to Q ≤ 46 ns max at VCC = 4.5 V.
16 VCC power_in Positive supply voltage; 2 V to 6 V (HC type) or 4.5 V to 5.5 V (HCT type); quiescent ICC ≤ 40 µA at VCC = 6 V, 85 °C.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: CD74HC109M96
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: cd74hc109m96-etched.step / cd74hc109m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hc109m96.step / cd74hc109m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (16 pp, sha256 3a88583aff8d86ad, retrieved 2026-09-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF