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Generated by kicad-footprint-generator · KiCad file format 20260206

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cd74hc08qm96ep-etched.step	cd74hc08qm96ep: factory component page (tier=lcsc) · Ray	17h ago
cd74hc08qm96ep-hero.glb	cd74hc08qm96ep: hero GLB from the etched model (keeps the MPN mark) · Ray	17h ago
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README.md	Initial commit: component/cd74hc08qm96ep · Ray	17h ago

CD74HC08QM96EP

Texas Instruments · Logic Gates · SOIC-14

CD74HC08QM96EP from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	1A	input	Input A of gate 1 (2-input AND gate, Y = A·B); input voltage range is 0 V to VCC, and unused inputs must be held at VCC or GND.
2	1B	input	Input B of gate 1 (2-input AND gate, Y = A·B); input voltage range is 0 V to VCC, and unused inputs must be held at VCC or GND.
3	1Y	output	Output of gate 1 (Y = A·B); standard output rated for 10 LSTTL loads over the temperature range.
4	2A	input	Input A of gate 2 (2-input AND gate, Y = A·B); input voltage range is 0 V to VCC, and unused inputs must be held at VCC or GND.
5	2B	input	Input B of gate 2 (2-input AND gate, Y = A·B); input voltage range is 0 V to VCC, and unused inputs must be held at VCC or GND.
6	2Y	output	Output of gate 2 (Y = A·B); standard output rated for 10 LSTTL loads over the temperature range.
7	GND	power_in	Ground reference for the device; all unused inputs must be tied to VCC or GND.
8	3Y	output	Output of gate 3 (Y = A·B); standard output rated for 10 LSTTL loads over the temperature range.
9	3A	input	Input A of gate 3 (2-input AND gate, Y = A·B); input voltage range is 0 V to VCC, and unused inputs must be held at VCC or GND.
10	3B	input	Input B of gate 3 (2-input AND gate, Y = A·B); input voltage range is 0 V to VCC, and unused inputs must be held at VCC or GND.
11	4Y	output	Output of gate 4 (Y = A·B); standard output rated for 10 LSTTL loads over the temperature range.
12	4A	input	Input A of gate 4 (2-input AND gate, Y = A·B); input voltage range is 0 V to VCC, and unused inputs must be held at VCC or GND.
13	4B	input	Input B of gate 4 (2-input AND gate, Y = A·B); input voltage range is 0 V to VCC, and unused inputs must be held at VCC or GND.
14	VCC	power_in	Positive supply; recommended operating range 2 V to 6 V, absolute maximum 7 V.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-14
Category	Logic
Pins	14

CAD (KiCad official)

Symbol: CD74HC08QM96EP
Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
3D model: SOIC-14 (KiCad packages3D, STEP)
3D model files: cd74hc08qm96ep-etched.step / cd74hc08qm96ep-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hc08qm96ep.step / cd74hc08qm96ep.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (12 pp, sha256 747f7afb36e8669d, retrieved 2026-10-08, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF