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CD74HC08QM96EP
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Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+50@@ -0,0 +1,50 @@+# CD74HC08QM96EP++**Texas Instruments** · Logic Gates · SOIC-14++CD74HC08QM96EP from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1A | input | Input A of gate 1 (2-input AND gate, Y = A·B); input voltage range is 0 V to VCC, and unused inputs must be held at VCC or GND. |+| 2 | 1B | input | Input B of gate 1 (2-input AND gate, Y = A·B); input voltage range is 0 V to VCC, and unused inputs must be held at VCC or GND. |+| 3 | 1Y | output | Output of gate 1 (Y = A·B); standard output rated for 10 LSTTL loads over the temperature range. |+| 4 | 2A | input | Input A of gate 2 (2-input AND gate, Y = A·B); input voltage range is 0 V to VCC, and unused inputs must be held at VCC or GND. |+| 5 | 2B | input | Input B of gate 2 (2-input AND gate, Y = A·B); input voltage range is 0 V to VCC, and unused inputs must be held at VCC or GND. |+| 6 | 2Y | output | Output of gate 2 (Y = A·B); standard output rated for 10 LSTTL loads over the temperature range. |+| 7 | GND | power_in | Ground reference for the device; all unused inputs must be tied to VCC or GND. |+| 8 | 3Y | output | Output of gate 3 (Y = A·B); standard output rated for 10 LSTTL loads over the temperature range. |+| 9 | 3A | input | Input A of gate 3 (2-input AND gate, Y = A·B); input voltage range is 0 V to VCC, and unused inputs must be held at VCC or GND. |+| 10 | 3B | input | Input B of gate 3 (2-input AND gate, Y = A·B); input voltage range is 0 V to VCC, and unused inputs must be held at VCC or GND. |+| 11 | 4Y | output | Output of gate 4 (Y = A·B); standard output rated for 10 LSTTL loads over the temperature range. |+| 12 | 4A | input | Input A of gate 4 (2-input AND gate, Y = A·B); input voltage range is 0 V to VCC, and unused inputs must be held at VCC or GND. |+| 13 | 4B | input | Input B of gate 4 (2-input AND gate, Y = A·B); input voltage range is 0 V to VCC, and unused inputs must be held at VCC or GND. |+| 14 | VCC | power_in | Positive supply; recommended operating range 2 V to 6 V, absolute maximum 7 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-14 |+| Category | Logic |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `CD74HC08QM96EP`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOIC-14 (KiCad packages3D, STEP)+- 3D model files: `cd74hc08qm96ep-etched.step` / `cd74hc08qm96ep-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74hc08qm96ep.step` / `cd74hc08qm96ep.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd74hc08-ep) (12 pp, sha256 `747f7afb36e8669d`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd74hc08qm96ep-datasheet.pdf)
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input voltage range is 0 V to VCC, and unused inputs must be held at VCC or GND."+ },+ {+ "number": "2",+ "name": "1B",+ "type": "input",+ "description": "Input B of gate 1 (2-input AND gate, Y = A·B); input voltage range is 0 V to VCC, and unused inputs must be held at VCC or GND."+ },+ {+ "number": "3",+ "name": "1Y",+ "type": "output",+ "description": "Output of gate 1 (Y = A·B); standard output rated for 10 LSTTL loads over the temperature range."+ },+ {+ "number": "4",+ "name": "2A",+ "type": "input",+ "description": "Input A of gate 2 (2-input AND gate, Y = A·B); input voltage range is 0 V to VCC, and unused inputs must be held at VCC or GND."+ },+ {+ "number": "5",+ "name": "2B",+ "type": "input",+ "description": "Input B of gate 2 (2-input AND gate, Y = A·B); input voltage range is 0 V to VCC, and unused inputs must be held at VCC or GND."+ },+ {+ "number": "6",+ "name": "2Y",+ "type": "output",+ "description": "Output of gate 2 (Y = A·B); standard output rated for 10 LSTTL loads over the temperature range."+ },+ {+ "number": "7",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for the device; all unused inputs must be tied to VCC or GND."+ },+ {+ "number": "8",+ "name": "3Y",+ "type": "output",+ "description": "Output of gate 3 (Y = A·B); standard output rated for 10 LSTTL loads over the temperature range."+ },+ {+ "number": "9",+ "name": "3A",+ "type": "input",+ "description": "Input A of gate 3 (2-input AND gate, Y = A·B); input voltage range is 0 V to VCC, and unused inputs must be held at VCC or GND."+ },+ {+ "number": "10",+ "name": "3B",+ "type": "input",+ "description": "Input B of gate 3 (2-input AND gate, Y = A·B); input voltage range is 0 V to VCC, and unused inputs must be held at VCC or GND."+ },+ {+ "number": "11",+ "name": "4Y",+ "type": "output",+ "description": "Output of gate 4 (Y = A·B); standard output rated for 10 LSTTL loads over the temperature range."+ },+ {+ "number": "12",+ "name": "4A",+ "type": "input",+ "description": "Input A of gate 4 (2-input AND gate, Y = A·B); input voltage range is 0 V to VCC, and unused inputs must be held at VCC or GND."+ },+ {+ "number": "13",+ "name": "4B",+ "type": "input",+ "description": "Input B of gate 4 (2-input AND gate, Y = A·B); input voltage range is 0 V to VCC, and unused inputs must be held at VCC or GND."+ },+ {+ "number": "14",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply; recommended operating range 2 V to 6 V, absolute maximum 7 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pin-to-name mapping was taken from the text layout of the pin diagram (numbers 1-7 then 14-8 listed ; Pin descriptions for gate inputs/outputs are derived from the function table (Y = A·B: H H to H, L X"+ ],+ "pages_sent": 12,+ "cost_usd": 0.0574,+ "at": "2026-10-08T19:32:14"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/cd74hc08-ep",+ "pages": 12,+ "sha256": "747f7afb36e8669d",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "cd74hc08qm96ep.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 8.7,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "cd74hc08qm96ep-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 8.7,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "fa3a4dbc129768ac3f2a81df69363fd4df77b3ba814dfc4b7caaa29b86cce2db",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}