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cd74hc00m96

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Texas Instruments Gates, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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CD74HC00M96

Texas Instruments · Gates · SOIC-14

CD74HC00M96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Gate 1 input A. CMOS logic input, VIH = 3.15 V min at VCC = 4.5 V; input leakage ±1 µA max. Buffered input to the first 2-input NAND gate.
2 1B input Gate 1 input B. CMOS logic input, VIH = 3.15 V min at VCC = 4.5 V; input leakage ±1 µA max. Buffered input to the first 2-input NAND gate.
3 1Y output Gate 1 output. Y = NOT(1A AND 1B). CMOS push-pull output; VOH ≥ 3.98 V typ, VOL ≤ 0.26 V typ at IO = ±4 mA, VCC = 4.5 V. Drives 10 LSTTL loads.
4 2A input Gate 2 input A. CMOS logic input, VIH = 3.15 V min at VCC = 4.5 V; input leakage ±1 µA max. Buffered input to the second 2-input NAND gate.
5 2B input Gate 2 input B. CMOS logic input, VIH = 3.15 V min at VCC = 4.5 V; input leakage ±1 µA max. Buffered input to the second 2-input NAND gate.
6 2Y output Gate 2 output. Y = NOT(2A AND 2B). CMOS push-pull output; VOH ≥ 3.98 V typ, VOL ≤ 0.26 V typ at IO = ±4 mA, VCC = 4.5 V. Drives 10 LSTTL loads.
7 GND power_in Ground reference (0 V). Common return for all four NAND gates and internal logic.
8 3Y output Gate 3 output. Y = NOT(3A AND 3B). CMOS push-pull output; VOH ≥ 3.98 V typ, VOL ≤ 0.26 V typ at IO = ±4 mA, VCC = 4.5 V. Drives 10 LSTTL loads.
9 3A input Gate 3 input A. CMOS logic input, VIH = 3.15 V min at VCC = 4.5 V; input leakage ±1 µA max. Buffered input to the third 2-input NAND gate.
10 3B input Gate 3 input B. CMOS logic input, VIH = 3.15 V min at VCC = 4.5 V; input leakage ±1 µA max. Buffered input to the third 2-input NAND gate.
11 4Y output Gate 4 output. Y = NOT(4A AND 4B). CMOS push-pull output; VOH ≥ 3.98 V typ, VOL ≤ 0.26 V typ at IO = ±4 mA, VCC = 4.5 V. Drives 10 LSTTL loads.
12 4A input Gate 4 input A. CMOS logic input, VIH = 3.15 V min at VCC = 4.5 V; input leakage ±1 µA max. Buffered input to the fourth 2-input NAND gate.
13 4B input Gate 4 input B. CMOS logic input, VIH = 3.15 V min at VCC = 4.5 V; input leakage ±1 µA max. Buffered input to the fourth 2-input NAND gate.
14 VCC power_in Positive supply. HC types operate 2 V to 6 V; HCT types 4.5 V to 5.5 V. Quiescent ICC ≤ 2 µA typ at 25 °C. Decouple to GND with a local 0.1 µF ceramic capacitor.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Logic
Pins 14

Ordering variants

  • CD74HC00M96
  • CD74HC00M96M
  • CD74HC00M96MT
  • CD74HC00M96E
  • CD74HC00M96F3A

CAD (KiCad official)

  • Symbol: CD74HC00M96
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: cd74hc00m96-etched.step / cd74hc00m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hc00m96.step / cd74hc00m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (None pp, sha256 df0eb3a906630b2b, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF