# CD74ACT74M96

**Texas Instruments** · Logic ICs · SOIC-14

CD74ACT74M96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1CLR | input | Active-low asynchronous clear for flip-flop 1; a low level resets the outputs regardless of the levels of the other inputs. |
| 2 | 1D | input | Data input for flip-flop 1; data meeting the setup time requirement is transferred to the outputs on the positive-going clock edge. |
| 3 | 1CLK | input | Positive-edge clock input for flip-flop 1; clock triggering occurs at a voltage level and is not directly related to the clock pulse rise time. |
| 4 | 1PRE | input | Active-low asynchronous preset for flip-flop 1; a low level sets the outputs regardless of the levels of the other inputs. |
| 5 | 1Q | output | True output of flip-flop 1. |
| 6 | 1Q | output | Complementary (inverted) output of flip-flop 1; printed as 1Q with an overbar in the datasheet. |
| 7 | GND | power_in | Ground reference pin for the device. |
| 8 | 2Q | output | Complementary (inverted) output of flip-flop 2; printed as 2Q with an overbar in the datasheet. |
| 9 | 2Q | output | True output of flip-flop 2. |
| 10 | 2PRE | input | Active-low asynchronous preset for flip-flop 2; a low level sets the outputs regardless of the levels of the other inputs. |
| 11 | 2CLK | input | Positive-edge clock input for flip-flop 2; clock triggering occurs at a voltage level and is not directly related to the clock pulse rise time. |
| 12 | 2D | input | Data input for flip-flop 2; data meeting the setup time requirement is transferred to the outputs on the positive-going clock edge. |
| 13 | 2CLR | input | Active-low asynchronous clear for flip-flop 2; a low level resets the outputs regardless of the levels of the other inputs. |
| 14 | VCC | power_in | Supply voltage pin; recommended operating supply range is 4.5 V to 5.5 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic ICs |
| Pins | 14 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 4.5 |  | 5.5 | V | TA = -55°C to 125°C | 2 |
| High-level input voltage | VIH | 2 |  |  | V | TA = -55°C to 125°C | 2 |
| Low-level input voltage | VIL |  |  | 0.8 | V | TA = -55°C to 125°C | 2 |
| Input voltage | VI | 0 |  |  | V | TA = -55°C to 125°C | 2 |
| Output voltage | VO | 0 |  |  | V | TA = -55°C to 125°C | 2 |
| High-level output current | IOH | -24 |  |  | mA | TA = -55°C to 125°C | 2 |
| Low-level output current | IOL |  |  | 24 | mA | TA = -55°C to 125°C | 2 |
| Input transition rise or fall rate | Δt/Δv |  |  | 10 | ns/V | TA = -55°C to 125°C | 2 |
| Operating free-air temperature range | TA | -55 |  | 125 | °C | CD74ACT74M (SOIC M package), per ordering information | 1 |
| Supply voltage range | VCC | -0.5 |  | 6 | V |  | 2 |
| Input clamp current | IIK | -20 |  | 20 | mA | VI < 0 or VI > VCC | 2 |
| Output clamp current | IOK | -50 |  | 50 | mA | VO < 0 or VO > VCC | 2 |
| Continuous output current | IO | -50 |  | 50 | mA | VO = 0 to VCC | 2 |
| Continuous current through VCC or GND |  | -100 |  | 100 | mA |  | 2 |
| Storage temperature range | Tstg | -65 |  | 150 | °C |  | 2 |
| High-level output voltage | VOH | 4.4 |  |  | V | IOH = -50 µA, VI = VIH or VIL, VCC = 4.5 V, TA = 25°C | 3 |
| High-level output voltage | VOH | 3.94 |  |  | V | IOH = -24 mA, VI = VIH or VIL, VCC = 4.5 V, TA = 25°C | 3 |
| High-level output voltage | VOH | 3.7 |  |  | V | IOH = -24 mA, VI = VIH or VIL, VCC = 4.5 V, TA = -55°C to 125°C | 3 |
| High-level output voltage | VOH | 3.85 |  |  | V | IOH = -50 mA†, VCC = 5.5 V | 3 |
| Low-level output voltage | VOL |  |  | 0.1 | V | IOL = 50 µA, VI = VIH or VIL, VCC = 4.5 V, TA = 25°C | 3 |
| Low-level output voltage | VOL |  |  | 0.36 | V | IOL = 24 mA, VI = VIH or VIL, VCC = 4.5 V, TA = 25°C | 3 |
| Low-level output voltage | VOL |  |  | 0.5 | V | IOL = 24 mA, VI = VIH or VIL, VCC = 4.5 V, TA = -55°C to 125°C | 3 |
| Low-level output voltage | VOL |  |  | 1.65 | V | IOL = 50 mA†, VCC = 5.5 V | 3 |
| Input current | II | -0.1 |  | 0.1 | µA | VI = VCC or GND, VCC = 5.5 V, TA = 25°C | 3 |
| Input current | II | -1 |  | 1 | µA | VI = VCC or GND, VCC = 5.5 V, TA = -55°C to 125°C | 3 |
| Quiescent supply current | ICC |  |  | 4 | µA | VI = VCC or GND, IO = 0, VCC = 5.5 V, TA = 25°C | 3 |
| Quiescent supply current | ICC |  |  | 80 | µA | VI = VCC or GND, IO = 0, VCC = 5.5 V, TA = -55°C to 125°C | 3 |
| Additional quiescent supply current per input pin | ICC‡ |  |  | 2.4 | mA | VI = VCC, 2.1 V, VCC = 4.5 V to 5.5 V, TA = 25°C | 3 |
| Additional quiescent supply current per input pin | ICC‡ |  |  | 3 | mA | VI = VCC, 2.1 V, VCC = 4.5 V to 5.5 V, TA = -55°C to 125°C | 3 |
| Input capacitance | Ci |  |  | 10 | pF |  | 3 |
| Clock frequency | fclock | 85 |  |  | MHz | VCC = 5 V ± 0.5 V, TA = -55°C to 125°C | 3 |
| Pulse duration, PRE or CLR low | tw | 5 |  |  | ns | VCC = 5 V ± 0.5 V, TA = -55°C to 125°C | 3 |
| Pulse duration, CLK | tw | 5.7 |  |  | ns | VCC = 5 V ± 0.5 V, TA = -55°C to 125°C | 3 |
| Setup time, data | tsu | 4 |  |  | ns | VCC = 5 V ± 0.5 V, TA = -55°C to 125°C | 3 |
| Hold time, data after CLK↑ | th | 0 |  |  | ns | VCC = 5 V ± 0.5 V, TA = -55°C to 125°C | 3 |
| Recovery time, before CLK↑, CLR↑ or PRE↑ | trec | 2.7 |  |  | ns | VCC = 5 V ± 0.5 V, TA = -55°C to 125°C | 3 |
| Maximum clock frequency | fmax | 85 |  |  | MHz | VCC = 5 V ± 0.5 V, TA = -55°C to 125°C | 4 |
| Propagation delay, CLK to Q or Q (tPLH) | tPLH | 2.4 |  | 9.5 | ns | VCC = 5 V ± 0.5 V, TA = -55°C to 125°C | 4 |
| Propagation delay, CLK to Q or Q (tPHL) | tPHL | 2.4 |  | 9.5 | ns | VCC = 5 V ± 0.5 V, TA = -55°C to 125°C | 4 |
| Propagation delay, PRE or CLR to Q or Q (tPLH) | tPLH | 2.9 |  | 11.5 | ns | VCC = 5 V ± 0.5 V, TA = -55°C to 125°C | 4 |
| Propagation delay, PRE or CLR to Q or Q (tPHL) | tPHL | 3.1 |  | 12.5 | ns | VCC = 5 V ± 0.5 V, TA = -55°C to 125°C | 4 |
| Package thermal impedance, M package (SOIC) | θJA |  | 86 |  | °C/W | JESD 51-7 (see Note 2) | 2 |

## CAD (KiCad official)

- Symbol: `CD74ACT74M96`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files: `cd74act74m96-etched.step` / `cd74act74m96-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74act74m96.step` / `cd74act74m96.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cd74act74m96.pdf) (17 pp, sha256 `98a4fb0885160cd9`, retrieved 2026-10-17, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cd74act74m96-datasheet.pdf)