component
CD74ACT299M96
Public Made by Adomby adom
Texas Instruments Shift Registers, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"number": "1",
"name": "S0",
"type": "input",
"description": "Mode select 0; together with S1 selects hold, shift right, shift left or parallel load, and when S0 and S1 are both high the I/O pins are high-impedance inputs."
},
{
"number": "2",
"name": "!OE1",
"type": "input",
"description": "Active-low output enable 1; when high the I/O terminals are forced to the off (high-impedance) state."
},
{
"number": "3",
"name": "!OE2",
"type": "input",
"description": "Active-low output enable 2; when high the I/O terminals are forced to the off (high-impedance) state."
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{
"number": "4",
"name": "I/O6",
"type": "bidirectional",
"description": "Parallel data input/output 6, a three-state output and CMOS-buffered input."
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{
"number": "5",
"name": "I/O4",
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{
"number": "6",
"name": "I/O2",
"type": "bidirectional",
"description": "Parallel data input/output 2, a three-state output and CMOS-buffered input."
},
{
"number": "7",
"name": "I/O0",
"type": "bidirectional",
"description": "Parallel data input/output 0, a three-state output and CMOS-buffered input."
},
{
"number": "8",
"name": "Q0",
"type": "output",
"description": "Serial output from the first register stage, used for cascading to the DS7 input of the previous register."
},
{
"number": "9",
"name": "!MR",
"type": "input",
"description": "Master reset, active low; on the 299 it asynchronously clears the register regardless of all other inputs."
},
{
"number": "10",
"name": "GND",
"type": "power_in",
"description": "Ground."
},
{
"number": "11",
"name": "DS0",
"type": "input",
"description": "Serial data input for right shift, sampled on the low-to-high transition of CP."
},
{
"number": "12",
"name": "CP",
"type": "input",
"description": "Clock input, rising-edge triggered; mode select, serial data and parallel data respond only to its low-to-high transition."
},
{
"number": "13",
"name": "I/O1",
"type": "bidirectional",
"description": "Parallel data input/output 1, a three-state output and CMOS-buffered input."
},
{
"number": "14",
"name": "I/O3",
"type": "bidirectional",
"description": "Parallel data input/output 3, a three-state output and CMOS-buffered input."
},
{
"number": "15",
"name": "I/O5",
"type": "bidirectional",
"description": "Parallel data input/output 5, a three-state output and CMOS-buffered input."
},
{
"number": "16",
"name": "I/O7",
"type": "bidirectional",
"description": "Parallel data input/output 7, a three-state output and CMOS-buffered input."
},
{
"number": "17",
"name": "Q7",
"type": "output",
"description": "Serial output from the last register stage, used for cascading to the DS0 input of the next register."
},
{
"number": "18",
"name": "DS7",
"type": "input",
"description": "Serial data input for left shift, sampled on the low-to-high transition of CP."
},
{
"number": "19",
"name": "S1",
"type": "input",
"description": "Mode select 1; together with S0 selects hold, shift right, shift left or parallel load."
},
{
"number": "20",
"name": "VCC",
"type": "power_in",
"description": "Positive supply; 4.5 V to 5.5 V recommended for ACT types, with a 0.1 µF bypass capacitor placed close to the pin."
}
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"at": "2026-10-11T20:41:06"
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"Package": "SOIC-20-300mil",
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