component

CD74ACT163M96

Public Made by Adom

by adom

Texas Instruments Counters, Dividers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogiccd74act163m96factory-2.0.0extractor-text

Verified CD74ACT163M96

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CD74ACT163M96 · SOIC-16 · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 18-page datasheet
  • ✓distributor: lcsc C2675449, digikey 296-31552-2-ND, mouser 595-CD74ACT163M96
  • ✓family: SOIC-16_3.9x9.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-p6i6qcje/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cd74act163m96.kicad_sym✓ cd74act163m96.kicad_mod✓ cd74act163m96.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers cd74act163m96: viewers · Ray
cd74act163m96-etched.glb Publish 0.1.0 · Ray
cd74act163m96-etched.step cd74act163m96: factory component page (tier=mfr) · Ray
cd74act163m96-hero.glb cd74act163m96: hero GLB from the etched model (keeps the MPN mark) · Ray
cd74act163m96-hero.overlay.json Publish 0.1.0 · Ray
cd74act163m96.glb Publish 0.1.0 · Ray
cd74act163m96.kicad_mod Publish 0.1.0 · Ray
cd74act163m96.kicad_sym Publish 0.1.0 · Ray
cd74act163m96.lbr Publish 0.1.0 · Ray
cd74act163m96.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier mfr, 16 pins · Ray

CD74ACT163M96

Texas Instruments · Counters, Dividers · SOIC-16

CD74ACT163M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLR input Active-low synchronous clear; a low level sets all four flip-flop outputs low after the next low-to-high CLK transition, regardless of the enable inputs.
2 CLK input Buffered clock input; the four flip-flops trigger on the rising (positive-going) clock edge.
3 A input Parallel data input A, loaded into QA on the next CLK pulse when LOAD is low.
4 B input Parallel data input B, loaded into QB on the next CLK pulse when LOAD is low.
5 C input Parallel data input C, loaded into QC on the next CLK pulse when LOAD is low.
6 D input Parallel data input D, loaded into QD on the next CLK pulse when LOAD is low.
7 ENP input Count-enable input; both ENP and ENT must be high to count, and transitions at ENP are allowed regardless of CLK.
8 GND power_in Ground reference for the device.
9 LOAD input Active-low synchronous preset; a low level disables the counter and causes the outputs to match the A-D setup data after the next clock pulse.
10 ENT input Count-enable input that is fed forward to enable RCO; both ENP and ENT must be high to count.
11 QD output Counter output bit D.
12 QC output Counter output bit C.
13 QB output Counter output bit B.
14 QA output Counter output bit A.
15 RCO output Ripple-carry output; produces a high-level pulse when ENT is high and the count is maximum (9 or 15, with QA high).
16 VCC power_in Supply voltage; recommended operating range is 4.5 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range VCC -0.5 6 V 6
Input clamp current IIK -20 20 mA VI < 0 or VI > VCC 6
Output clamp current IOK -50 50 mA VO < 0 or VO > VCC 6
Continuous output current IO -50 50 mA VO = 0 to VCC 6
Continuous current through VCC or GND -100 100 mA 6
Storage temperature range Tstg -65 150 °C 6
Package thermal impedance, M package θJA 73 °C/W Per JESD 51-7 6
Supply voltage VCC 4.5 5.5 V 6
High-level input voltage VIH 2 V 6
Low-level input voltage VIL 0.8 V 6
Input voltage VI 0 V 0 to VCC 6
Output voltage VO 0 V 0 to VCC 6
High-level output current IOH -24 mA 6
Low-level output current IOL 24 mA 6
Input transition rise or fall rate ∆t/∆v 10 ns 6
High-level output voltage VOH 3.7 V IOH = -24 mA; VI = VIH or VIL; VCC 4.5 V 7
High-level output voltage VOH 4.4 V IOH = -50 µA; VI = VIH or VIL; VCC 4.5 V 7
High-level output voltage VOH 3.85 V IOH = -50 mA; VCC 5.5 V; one output at a time 7
Low-level output voltage VOL 0.1 V IOL = 50 µA; VI = VIH or VIL; VCC 4.5 V 7
Low-level output voltage VOL 0.5 V IOL = 24 mA; VI = VIH or VIL; VCC 4.5 V 7
Low-level output voltage VOL 1.65 V IOL = 50 mA; VCC 5.5 V; one output at a time 7
Input current II -1 1 µA VI = VCC or GND; 5.5 V 7
Quiescent supply current ICC 160 µA VI = VCC or GND, IO = 0; 5.5 V 7
Additional quiescent supply current per input pin ICC 3 mA VI = VCC -2.1 V; 4.5 V to 5.5 V 7
Clock frequency fclock 80 MHz 7
Pulse duration CLK high or low tw 6.2 ns 7
Setup time before CLK↑, A, B, C, or D tsu 5 ns 7
Setup time before CLK↑, ENP or ENT tsu 6 ns 7
Setup time before CLK↑, LOAD low tsu 7.5 ns 7
Setup time before CLK↑, CLR inactive tsu 7.5 ns 7
Hold time after CLK↑, A, B, C, or D th 0 ns 7
Hold time after CLK↑, ENP or ENT th 0 ns 7
Hold time after CLK↑, LOAD low th 0 ns 7
Hold time after CLK↑, CLR inactive th 0 ns 7
Maximum clock frequency fmax 80 MHz CL = 50 pF 8
Propagation delay CLK to RCO tpd 4.2 16.7 ns CL = 50 pF 8
Propagation delay CLK to any Q tpd 4.1 16.5 ns CL = 50 pF 8
Propagation delay ENT to RCO tpd 2.7 10.8 ns CL = 50 pF 8
Power dissipation capacitance Cpd 66 pF No load 8

CAD (KiCad official)

  • Symbol: CD74ACT163M96
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: cd74act163m96-etched.step / cd74act163m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74act163m96.step / cd74act163m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (18 pp, sha256 31f97fb1a5d91e1a, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF