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CD74ACT151M96
Public Made by Adomby adom
Texas Instruments Signal Switches, Multiplexers, Decoders, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD74ACT151M96
Texas Instruments · Signal Switches, Multiplexers, Decoders · SOIC-16
CD74ACT151M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | D3 | input | Data input 3 of the eight data sources; its level is routed to Y and W when the A/B/C select code addresses it and G is low. |
| 2 | D2 | input | Data input 2 of the eight data sources; its level is routed to Y and W when the A/B/C select code addresses it and G is low. |
| 3 | D1 | input | Data input 1 of the eight data sources; its level is routed to Y and W when the A/B/C select code addresses it and G is low. |
| 4 | D0 | input | Data input 0 of the eight data sources; its level is routed to Y and W when the A/B/C select code addresses it and G is low. |
| 5 | Y | output | Multiplexer output that carries the selected data input level and is forced low when strobe G is high. |
| 6 | W | output | Multiplexer output that carries the selected data input level and is forced high when strobe G is high. |
| 7 | G | input | Active-low strobe that must be at a low logic level to enable the data inputs; a high level forces W high and Y low. |
| 8 | GND | power_in | Ground reference for the device. |
| 9 | C | input | Binary select input (most significant bit of the 3-bit select code) that chooses which of D0-D7 is routed to the outputs. |
| 10 | B | input | Binary select input (middle bit of the 3-bit select code) that chooses which of D0-D7 is routed to the outputs. |
| 11 | A | input | Binary select input (least significant bit of the 3-bit select code) that chooses which of D0-D7 is routed to the outputs. |
| 12 | D7 | input | Data input 7 of the eight data sources; its level is routed to Y and W when the A/B/C select code addresses it and G is low. |
| 13 | D6 | input | Data input 6 of the eight data sources; its level is routed to Y and W when the A/B/C select code addresses it and G is low. |
| 14 | D5 | input | Data input 5 of the eight data sources; its level is routed to Y and W when the A/B/C select code addresses it and G is low. |
| 15 | D4 | input | Data input 4 of the eight data sources; its level is routed to Y and W when the A/B/C select code addresses it and G is low. |
| 16 | VCC | power_in | Supply voltage; recommended operating range is 4.5 V to 5.5 V, with an absolute maximum of 6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 4.5 | 5.5 | V | 3 | ||
| High-level input voltage | VIH | 2 | V | 3 | |||
| Low-level input voltage | VIL | 0.8 | V | 3 | |||
| Input voltage | VI | 0 | V | Maximum printed as VCC | 3 | ||
| Output voltage | VO | 0 | V | Maximum printed as VCC | 3 | ||
| High-level output current | IOH | -24 | mA | 3 | |||
| Low-level output current | IOL | 24 | mA | 3 | |||
| Input transition rise or fall rate | ∆t/∆v | 10 | ns/V | 3 | |||
| Operating free-air temperature range (orderable CD74ACT151M96) | TA | -55 | 125 | °C | Orderable part CD74ACT151M96, SOIC, tape and reel | 1 | |
| Supply voltage range | VCC | -0.5 | 6 | V | 2 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI < 0 V or VI > VCC (see Note 1) | 2 | |
| Output clamp current | IOK | -50 | 50 | mA | VO < 0 V or VO > VCC (see Note 1) | 2 | |
| Continuous output current | IO | -50 | 50 | mA | VO > 0 V or VO < VCC | 2 | |
| Continuous current through VCC or GND | -100 | 100 | mA | 2 | |||
| Package thermal impedance | θJA | 73 | °C/W | See Note 2 (JESD 51-7) | 2 | ||
| Storage temperature range | Tstg | -65 | 150 | °C | 2 | ||
| High-level output voltage | VOH | 4.4 | V | VI = VIH or VIL; IOH = -50 µA; VCC = 4.5 V; TA = -55°C to 125°C | 3 | ||
| High-level output voltage | VOH | 3.7 | V | VI = VIH or VIL; IOH = -24 mA; VCC = 4.5 V; TA = -55°C to 125°C | 3 | ||
| High-level output voltage | VOH | 3.85 | V | VI = VIH or VIL; IOH = -75 mA† ; VCC = 5.5 V; TA = -55°C to 125°C | 3 | ||
| Low-level output voltage | VOL | 0.1 | V | VI = VIH or VIL; IOL = 50 µA; VCC = 4.5 V; TA = -55°C to 125°C | 3 | ||
| Low-level output voltage | VOL | 0.5 | V | VI = VIH or VIL; IOL = 24 mA; VCC = 4.5 V; TA = -55°C to 125°C | 3 | ||
| Low-level output voltage | VOL | 1.65 | V | VI = VIH or VIL; IOL = 75 mA† ; VCC = 5.5 V; TA = -55°C to 125°C | 3 | ||
| Input leakage current | II | -1 | 1 | µA | VI = VCC or GND; VCC = 5.5 V; TA = -55°C to 125°C | 3 | |
| Quiescent supply current | ICC | 160 | µA | VI = VCC or GND, IO = 0; VCC = 5.5 V; TA = -55°C to 125°C | 3 | ||
| Additional quiescent supply current per input pin | ICC‡ | 3 | mA | VI = VCC, 2.1 V; VCC = 4.5 V to 5.5 V; TTL inputs high, 1 unit load; TA = -55°C to 125°C | 3 | ||
| Propagation delay D to Y, low-to-high | tPLH | 3.9 | 15.5 | ns | VCC = 5 V ± 0.5 V, CL = 50 pF; TA = -55°C to 125°C | 4 | |
| Propagation delay D to Y, high-to-low | tPHL | 3.9 | 15.5 | ns | VCC = 5 V ± 0.5 V, CL = 50 pF; TA = -55°C to 125°C | 4 | |
| Propagation delay D to W, low-to-high | tPLH | 4.2 | 16.9 | ns | VCC = 5 V ± 0.5 V, CL = 50 pF; TA = -55°C to 125°C | 4 | |
| Propagation delay D to W, high-to-low | tPHL | 4.2 | 16.9 | ns | VCC = 5 V ± 0.5 V, CL = 50 pF; TA = -55°C to 125°C | 4 | |
| Propagation delay A, B or C to Y, low-to-high | tPLH | 5.1 | 20.2 | ns | VCC = 5 V ± 0.5 V, CL = 50 pF; TA = -55°C to 125°C | 4 | |
| Propagation delay A, B or C to Y, high-to-low | tPHL | 5.1 | 20.2 | ns | VCC = 5 V ± 0.5 V, CL = 50 pF; TA = -55°C to 125°C | 4 | |
| Propagation delay A, B or C to W, low-to-high | tPLH | 5.4 | 21.6 | ns | VCC = 5 V ± 0.5 V, CL = 50 pF; TA = -55°C to 125°C | 4 | |
| Propagation delay A, B or C to W, high-to-low | tPHL | 5.4 | 21.6 | ns | VCC = 5 V ± 0.5 V, CL = 50 pF; TA = -55°C to 125°C | 4 | |
| Propagation delay G to Y, low-to-high | tPLH | 3 | 12.1 | ns | VCC = 5 V ± 0.5 V, CL = 50 pF; TA = -55°C to 125°C | 4 | |
| Propagation delay G to Y, high-to-low | tPHL | 3 | 12.1 | ns | VCC = 5 V ± 0.5 V, CL = 50 pF; TA = -55°C to 125°C | 4 | |
| Propagation delay G to W, low-to-high | tPLH | 3.4 | 13.5 | ns | VCC = 5 V ± 0.5 V, CL = 50 pF; TA = -55°C to 125°C | 4 | |
| Propagation delay G to W, high-to-low | tPHL | 3.4 | 13.5 | ns | VCC = 5 V ± 0.5 V, CL = 50 pF; TA = -55°C to 125°C | 4 |
CAD (KiCad official)
- Symbol:
CD74ACT151M96 - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
cd74act151m96-etched.step/cd74act151m96-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd74act151m96.step/cd74act151m96.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (13 pp, sha256
2a663121faea080f, retrieved 2026-10-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).