component
CD74ACT14E
Public Made by Adomby adom
Texas Instruments Inverters, PDIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CD74ACT14E
Texas Instruments · Inverters · PDIP-14
CD74ACT14E from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Input A of inverter channel 1; the datasheet specifies input voltage limits of 0 V to VCC in the recommended operating conditions. |
| 2 | 1Y | output | Output Y of inverter channel 1 (Y = A); the output is rated for ±24 mA drive current per the features list. |
| 3 | 2A | input | Input A of inverter channel 2; the input voltage must stay within 0 V to VCC per the recommended operating conditions. |
| 4 | 2Y | output | Output Y of inverter channel 2 (Y = A); the output is rated for ±24 mA drive current per the features list. |
| 5 | 3A | input | Input A of inverter channel 3; the input voltage must stay within 0 V to VCC per the recommended operating conditions. |
| 6 | 3Y | output | Output Y of inverter channel 3 (Y = A); the output is rated for ±24 mA drive current per the features list. |
| 7 | GND | power_in | Ground reference pin for the device. |
| 8 | 4Y | output | Output Y of inverter channel 4 (Y = A); the output is rated for ±24 mA drive current per the features list. |
| 9 | 4A | input | Input A of inverter channel 4; the input voltage must stay within 0 V to VCC per the recommended operating conditions. |
| 10 | 5Y | output | Output Y of inverter channel 5 (Y = A); the output is rated for ±24 mA drive current per the features list. |
| 11 | 5A | input | Input A of inverter channel 5; the input voltage must stay within 0 V to VCC per the recommended operating conditions. |
| 12 | 6Y | output | Output Y of inverter channel 6 (Y = A); the output is rated for ±24 mA drive current per the features list. |
| 13 | 6A | input | Input A of inverter channel 6; the input voltage must stay within 0 V to VCC per the recommended operating conditions. |
| 14 | VCC | power_in | Positive supply; the recommended supply range is 4.5 V to 5.5 V and the absolute maximum is 6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 6 | V | 4 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI < 0 or VI > VCC | 4 | |
| Output clamp current | IOK | -50 | 50 | mA | VO < 0 or VO > VCC | 4 | |
| Continuous output current | IO | -50 | 50 | mA | VO = 0 to VCC | 4 | |
| Continuous current through VCC or GND | -100 | 100 | mA | 4 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Supply voltage | VCC | 4.5 | 5.5 | V | Over recommended operating free-air temperature range | 4 | |
| Input voltage | VI | 0 | V | Over recommended operating free-air temperature range; max printed as VCC | 4 | ||
| Output voltage | VO | 0 | V | Over recommended operating free-air temperature range; max printed as VCC | 4 | ||
| High-level output current | IOH | -24 | mA | Over recommended operating free-air temperature range | 4 | ||
| Low-level output current | IOL | 24 | mA | Over recommended operating free-air temperature range | 4 | ||
| Input transition rise or fall rate | T∆t/∆v | 20 | °C | Over recommended operating free-air temperature range | 4 | ||
| Junction-to-ambient thermal resistance (N PDIP, 14 pins) | RθJA | 80 | °C/W | N (PDIP) 14 pins | 4 | ||
| Positive-going threshold | VT+ | 1.4 | 2 | V | VCC = 5 V; TA = 25°C | 4 | |
| Negative-going threshold | VT− | 0.8 | 1.3 | V | VCC = 5 V; TA = 25°C | 5 | |
| Hysteresis (VT+ − VT−) | ΔVT | 0.4 | V | VCC = 5 V; TA = 25°C | 5 | ||
| High-level output voltage | VOH | 4.4 | V | VI = VT+; IOH = −50 µA; VCC = 4.5 V; TA = 25°C | 5 | ||
| High-level output voltage | VOH | 3.94 | V | VI = VT+; IOH = −24 mA; VCC = 4.5 V; TA = 25°C | 5 | ||
| High-level output voltage | VOH | 3.7 | V | VI = VT+; IOH = −24 mA; VCC = 4.5 V; TA = −55°C to 125°C | 5 | ||
| High-level output voltage | VOH | 3.8 | V | VI = VT+; IOH = −24 mA; VCC = 4.5 V; TA = −40°C to 85°C | 5 | ||
| High-level output voltage | VOH | 3.85 | V | VI = VT+; IOH = −50 mA; VCC = 5.5 V; temperature column not determinable | 5 | ||
| Low-level output voltage | VOL | 0.1 | V | VI = VT−; IOL = 50 µA; VCC = 4.5 V; TA = 25°C | 5 | ||
| Low-level output voltage | VOL | 0.36 | V | VI = VT−; IOL = 24 mA; VCC = 4.5 V; TA = 25°C | 5 | ||
| Low-level output voltage | VOL | 0.5 | V | VI = VT−; IOL = 24 mA; VCC = 4.5 V; TA = −55°C to 125°C | 5 | ||
| Low-level output voltage | VOL | 0.44 | V | VI = VT−; IOL = 24 mA; VCC = 4.5 V; TA = −40°C to 85°C | 5 | ||
| Low-level output voltage | VOL | 1.65 | V | VI = VT−; IOL = 50 mA; VCC = 5.5 V; temperature column not determinable | 5 | ||
| Input current | II | -0.1 | 0.1 | µA | VI = VCC or GND; VCC = 5.5 V; TA = 25°C | 5 | |
| Input current | II | -1 | 1 | µA | VI = VCC or GND; VCC = 5.5 V; TA = −55°C to 125°C | 5 | |
| Quiescent supply current | ICC | 4 | µA | VI = VCC or GND; IO = 0; VCC = 5.5 V; TA = 25°C | 5 | ||
| Quiescent supply current | ICC | 80 | µA | VI = VCC or GND; IO = 0; VCC = 5.5 V; TA = −55°C to 125°C | 5 | ||
| Quiescent supply current | ICC | 40 | µA | VI = VCC or GND; IO = 0; VCC = 5.5 V; TA = −40°C to 85°C | 5 | ||
| Additional quiescent supply current per input pin | ΔICC | 2.4 | mA | VI = VCC − 2.1 V; VCC = 4.5 V to 5.5 V; TA = 25°C | 5 | ||
| Additional quiescent supply current per input pin | ΔICC | 3 | mA | VI = VCC − 2.1 V; VCC = 4.5 V to 5.5 V; TA = −55°C to 125°C | 5 | ||
| Additional quiescent supply current per input pin | ΔICC | 2.8 | mA | VI = VCC − 2.1 V; VCC = 4.5 V to 5.5 V; TA = −40°C to 85°C | 5 | ||
| Input capacitance | Ci | 10 | pF | TA = 25°C | 5 | ||
| Propagation delay, low-to-high (A to Y) | tPLH | 3.6 | 14.5 | ns | VCC = 5 V ± 0.5 V; TA = −55°C to 125°C | 5 | |
| Propagation delay, low-to-high (A to Y) | tPLH | 3.7 | 13.2 | ns | VCC = 5 V ± 0.5 V; TA = −40°C to 85°C | 5 | |
| Propagation delay, high-to-low (A to Y) | tPHL | 2.4 | 9.5 | ns | VCC = 5 V ± 0.5 V; TA = −55°C to 125°C | 5 | |
| Propagation delay, high-to-low (A to Y) | tPHL | 2.4 | 8.6 | ns | VCC = 5 V ± 0.5 V; TA = −40°C to 85°C | 5 |
CAD (KiCad official)
- Symbol:
CD74ACT14E - Footprint:
Package_DIP:DIP-14_W7.62mm - 3D model: PDIP-14 (KiCad packages3D, STEP)
- 3D model files:
cd74act14e-etched.step/cd74act14e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd74act14e.step/cd74act14e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (21 pp, sha256
636f0c6a545a6761, retrieved 2026-10-16, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CD74ACT14E
**Texas Instruments** · Inverters · PDIP-14
CD74ACT14E from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Input A of inverter channel 1; the datasheet specifies input voltage limits of 0 V to VCC in the recommended operating conditions. |
| 2 | 1Y | output | Output Y of inverter channel 1 (Y = A); the output is rated for ±24 mA drive current per the features list. |
| 3 | 2A | input | Input A of inverter channel 2; the input voltage must stay within 0 V to VCC per the recommended operating conditions. |
| 4 | 2Y | output | Output Y of inverter channel 2 (Y = A); the output is rated for ±24 mA drive current per the features list. |
| 5 | 3A | input | Input A of inverter channel 3; the input voltage must stay within 0 V to VCC per the recommended operating conditions. |
| 6 | 3Y | output | Output Y of inverter channel 3 (Y = A); the output is rated for ±24 mA drive current per the features list. |
| 7 | GND | power_in | Ground reference pin for the device. |
| 8 | 4Y | output | Output Y of inverter channel 4 (Y = A); the output is rated for ±24 mA drive current per the features list. |
| 9 | 4A | input | Input A of inverter channel 4; the input voltage must stay within 0 V to VCC per the recommended operating conditions. |
| 10 | 5Y | output | Output Y of inverter channel 5 (Y = A); the output is rated for ±24 mA drive current per the features list. |
| 11 | 5A | input | Input A of inverter channel 5; the input voltage must stay within 0 V to VCC per the recommended operating conditions. |
| 12 | 6Y | output | Output Y of inverter channel 6 (Y = A); the output is rated for ±24 mA drive current per the features list. |
| 13 | 6A | input | Input A of inverter channel 6; the input voltage must stay within 0 V to VCC per the recommended operating conditions. |
| 14 | VCC | power_in | Positive supply; the recommended supply range is 4.5 V to 5.5 V and the absolute maximum is 6 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-14 |
| Category | Logic |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | | 6 | V | | 4 |
| Input clamp current | IIK | -20 | | 20 | mA | VI < 0 or VI > VCC | 4 |
| Output clamp current | IOK | -50 | | 50 | mA | VO < 0 or VO > VCC | 4 |
| Continuous output current | IO | -50 | | 50 | mA | VO = 0 to VCC | 4 |
| Continuous current through VCC or GND | | -100 | | 100 | mA | | 4 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 4 |
| Supply voltage | VCC | 4.5 | | 5.5 | V | Over recommended operating free-air temperature range | 4 |
| Input voltage | VI | 0 | | | V | Over recommended operating free-air temperature range; max printed as VCC | 4 |
| Output voltage | VO | 0 | | | V | Over recommended operating free-air temperature range; max printed as VCC | 4 |
| High-level output current | IOH | -24 | | | mA | Over recommended operating free-air temperature range | 4 |
| Low-level output current | IOL | | | 24 | mA | Over recommended operating free-air temperature range | 4 |
| Input transition rise or fall rate | T∆t/∆v | | | 20 | °C | Over recommended operating free-air temperature range | 4 |
| Junction-to-ambient thermal resistance (N PDIP, 14 pins) | RθJA | | 80 | | °C/W | N (PDIP) 14 pins | 4 |
| Positive-going threshold | VT+ | 1.4 | | 2 | V | VCC = 5 V; TA = 25°C | 4 |
| Negative-going threshold | VT− | 0.8 | | 1.3 | V | VCC = 5 V; TA = 25°C | 5 |
| Hysteresis (VT+ − VT−) | ΔVT | 0.4 | | | V | VCC = 5 V; TA = 25°C | 5 |
| High-level output voltage | VOH | 4.4 | | | V | VI = VT+; IOH = −50 µA; VCC = 4.5 V; TA = 25°C | 5 |
| High-level output voltage | VOH | 3.94 | | | V | VI = VT+; IOH = −24 mA; VCC = 4.5 V; TA = 25°C | 5 |
| High-level output voltage | VOH | 3.7 | | | V | VI = VT+; IOH = −24 mA; VCC = 4.5 V; TA = −55°C to 125°C | 5 |
| High-level output voltage | VOH | 3.8 | | | V | VI = VT+; IOH = −24 mA; VCC = 4.5 V; TA = −40°C to 85°C | 5 |
| High-level output voltage | VOH | 3.85 | | | V | VI = VT+; IOH = −50 mA; VCC = 5.5 V; temperature column not determinable | 5 |
| Low-level output voltage | VOL | | | 0.1 | V | VI = VT−; IOL = 50 µA; VCC = 4.5 V; TA = 25°C | 5 |
| Low-level output voltage | VOL | | | 0.36 | V | VI = VT−; IOL = 24 mA; VCC = 4.5 V; TA = 25°C | 5 |
| Low-level output voltage | VOL | | | 0.5 | V | VI = VT−; IOL = 24 mA; VCC = 4.5 V; TA = −55°C to 125°C | 5 |
| Low-level output voltage | VOL | | | 0.44 | V | VI = VT−; IOL = 24 mA; VCC = 4.5 V; TA = −40°C to 85°C | 5 |
| Low-level output voltage | VOL | | | 1.65 | V | VI = VT−; IOL = 50 mA; VCC = 5.5 V; temperature column not determinable | 5 |
| Input current | II | -0.1 | | 0.1 | µA | VI = VCC or GND; VCC = 5.5 V; TA = 25°C | 5 |
| Input current | II | -1 | | 1 | µA | VI = VCC or GND; VCC = 5.5 V; TA = −55°C to 125°C | 5 |
| Quiescent supply current | ICC | | | 4 | µA | VI = VCC or GND; IO = 0; VCC = 5.5 V; TA = 25°C | 5 |
| Quiescent supply current | ICC | | | 80 | µA | VI = VCC or GND; IO = 0; VCC = 5.5 V; TA = −55°C to 125°C | 5 |
| Quiescent supply current | ICC | | | 40 | µA | VI = VCC or GND; IO = 0; VCC = 5.5 V; TA = −40°C to 85°C | 5 |
| Additional quiescent supply current per input pin | ΔICC | | | 2.4 | mA | VI = VCC − 2.1 V; VCC = 4.5 V to 5.5 V; TA = 25°C | 5 |
| Additional quiescent supply current per input pin | ΔICC | | | 3 | mA | VI = VCC − 2.1 V; VCC = 4.5 V to 5.5 V; TA = −55°C to 125°C | 5 |
| Additional quiescent supply current per input pin | ΔICC | | | 2.8 | mA | VI = VCC − 2.1 V; VCC = 4.5 V to 5.5 V; TA = −40°C to 85°C | 5 |
| Input capacitance | Ci | | | 10 | pF | TA = 25°C | 5 |
| Propagation delay, low-to-high (A to Y) | tPLH | 3.6 | | 14.5 | ns | VCC = 5 V ± 0.5 V; TA = −55°C to 125°C | 5 |
| Propagation delay, low-to-high (A to Y) | tPLH | 3.7 | | 13.2 | ns | VCC = 5 V ± 0.5 V; TA = −40°C to 85°C | 5 |
| Propagation delay, high-to-low (A to Y) | tPHL | 2.4 | | 9.5 | ns | VCC = 5 V ± 0.5 V; TA = −55°C to 125°C | 5 |
| Propagation delay, high-to-low (A to Y) | tPHL | 2.4 | | 8.6 | ns | VCC = 5 V ± 0.5 V; TA = −40°C to 85°C | 5 |
## CAD (KiCad official)
- Symbol: `CD74ACT14E`
- Footprint: `Package_DIP:DIP-14_W7.62mm`
- 3D model: PDIP-14 (KiCad packages3D, STEP)
- 3D model files: `cd74act14e-etched.step` / `cd74act14e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74act14e.step` / `cd74act14e.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd74act14) (21 pp, sha256 `636f0c6a545a6761`, retrieved 2026-10-16, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cd74act14e-datasheet.pdf)