# CD74ACT05PWR

**Texas Instruments** · Inverters · TSSOP-14

CD74ACT05PWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Input of inverter 1; inputs are TTL-voltage compatible and must not float. |
| 2 | 1Y | output | Open-drain output of inverter 1; requires an external pullup resistor to operate correctly. |
| 3 | 2A | input | Input of inverter 2; inputs are TTL-voltage compatible and must not float. |
| 4 | 2Y | output | Open-drain output of inverter 2; requires an external pullup resistor to operate correctly. |
| 5 | 3A | input | Input of inverter 3; inputs are TTL-voltage compatible and must not float. |
| 6 | 3Y | output | Open-drain output of inverter 3; requires an external pullup resistor to operate correctly. |
| 7 | GND | power_in | Ground pin; connect to the exposed thermal pad and to the PCB ground plane. |
| 8 | 4Y | output | Open-drain output of inverter 4; requires an external pullup resistor to operate correctly. |
| 9 | 4A | input | Input of inverter 4; inputs are TTL-voltage compatible and must not float. |
| 10 | 5Y | output | Open-drain output of inverter 5; requires an external pullup resistor to operate correctly. |
| 11 | 5A | input | Input of inverter 5; inputs are TTL-voltage compatible and must not float. |
| 12 | 6Y | output | Open-drain output of inverter 6; requires an external pullup resistor to operate correctly. |
| 13 | 6A | input | Input of inverter 6; inputs are TTL-voltage compatible and must not float. |
| 14 | VCC | power_in | Supply pin; operating supply range is 4.5 V to 5.5 V, bypassed with a 0.1 µF capacitor placed close to the pin. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage range | VCC | -0.5 |  | 6 | V |  | 4 |
| Input clamp current | IIK | -20 |  | 20 | mA | VI < 0 or VI > VCC | 4 |
| Output clamp current | IOK |  |  | -50 | mA | VO < 0 | 4 |
| Continuous current | IO | -50 |  | 50 | mA |  | 4 |
| Storage temperature range | Tstg | -65 |  | 150 | °C |  | 4 |
| Supply voltage | VCC | 4.5 |  | 5.5 | V |  | 4 |
| High-level input voltage | VIH | 2 |  |  | V |  | 4 |
| Low-level input voltage | VIL |  |  | 0.8 | V |  | 4 |
| Input voltage | VI | 0 |  |  | V | maximum is VCC | 4 |
| Output voltage | VO | 0 |  | 5.5 | V |  | 4 |
| Low-level output current | IOL |  |  | 24 | mA |  | 4 |
| Input transition rise or fall rate | Δt/Δv |  |  | 10 | ns/V |  | 4 |
| Junction-to-ambient thermal resistance | RθJA |  | 132.2 |  | °C/W | PW (TSSOP) package | 4 |
| Low-level output voltage | VOL |  |  | 0.36 | V | VI = VIH or VIL, IOL = 24 mA, VCC 4.5 V, TA = 25°C | 5 |
| Low-level output voltage | VOL |  |  | 0.44 | V | VI = VIH or VIL, IOL = 24 mA, VCC 4.5 V, -40°C to 85°C | 5 |
| Low-level output voltage | VOL |  |  | 0.5 | V | VI = VIH or VIL, IOL = 24 mA, VCC 4.5 V, -55°C to 125°C | 5 |
| Low-level output voltage | VOL |  |  | 0.1 | V | VI = VIH or VIL, IOL = 50 mA, VCC 4.5 V, TA = 25°C | 5 |
| Low-level output voltage | VOL |  |  | 1.65 | V | VI = VIH or VIL, IOL = 50 mA(1), VCC 5.5 V | 5 |
| Input current | II | -0.1 |  | 0.1 | μA | VI = VCC or GND, VCC 5.5 V, TA = 25°C | 5 |
| Input current | II | -1 |  | 1 | μA | VI = VCC or GND, VCC 5.5 V, -40°C to 85°C | 5 |
| Quiescent supply current | ICC |  |  | 4 | μA | VI = VCC or GND, IO = 0, VCC 5.5 V, TA = 25°C | 5 |
| Quiescent supply current | ICC |  |  | 40 | μA | VI = VCC or GND, IO = 0, VCC 5.5 V, -40°C to 85°C | 5 |
| Quiescent supply current | ICC |  |  | 80 | μA | VI = VCC or GND, IO = 0, VCC 5.5 V, -55°C to 125°C | 5 |
| Additional supply current per input pin | ΔICC |  |  | 2.4 | mA | VI = VCC, 2.1 V, VCC 4.5 V to 5.5 V, TA = 25°C | 5 |
| Additional supply current per input pin | ΔICC |  |  | 2.8 | mA | VI = VCC, 2.1 V, VCC 4.5 V to 5.5 V, -40°C to 85°C | 5 |
| Additional supply current per input pin | ΔICC |  |  | 3 | mA | VI = VCC, 2.1 V, VCC 4.5 V to 5.5 V, -55°C to 125°C | 5 |
| Propagation delay (output enable low) | tPZL | 2.4 |  | 8.5 | ns | VCC = 5 V ± 0.5 V, CL = 50 pF, -40°C to 85°C | 5 |
| Propagation delay (output enable low) | tPZL | 2.3 |  | 9.3 | ns | VCC = 5 V ± 0.5 V, CL = 50 pF, -55°C to 125°C | 5 |
| Propagation delay (output low to high-Z) | tPLZ | 2.8 |  | 9.8 | ns | VCC = 5 V ± 0.5 V, CL = 50 pF, -40°C to 85°C | 5 |
| Propagation delay (output low to high-Z) | tPLZ | 2.7 |  | 10.8 | ns | VCC = 5 V ± 0.5 V, CL = 50 pF, -55°C to 125°C | 5 |

## CAD (KiCad official)

- Symbol: `CD74ACT05PWR`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `cd74act05pwr-etched.step` / `cd74act05pwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74act05pwr.step` / `cd74act05pwr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cd74act05.pdf) (30 pp, sha256 `070d5e4a4377c437`, retrieved 2026-10-17, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cd74act05pwr-datasheet.pdf)