component
CD74AC74M96
Public Made by Adomby adom
Texas Instruments Flip Flops, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD74AC74M96
Texas Instruments · Flip Flops · SOIC-14
CD74AC74M96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1CLR | input | Channel 1 clear input (active low); resets outputs regardless of other input levels when driven low. |
| 2 | 1D | input | Channel 1 data input; transferred to outputs on positive-edge clock trigger when PRE and CLR are inactive. |
| 3 | 1CLK | input | Channel 1 positive-edge triggered clock input; positive-going edge triggers data transfer. |
| 4 | 1PRE | input | Channel 1 preset input (active low); sets outputs regardless of other input levels when driven low. |
| 5 | 1Q | output | Channel 1 output; direct flip-flop output, driven by positive-edge clock or PRE/CLR inputs. |
| 6 | 1Q̄ | output | Channel 1 inverted output; complement of Q output, driven by positive-edge clock or PRE/CLR inputs. |
| 7 | GND | power_in | Ground; circuit reference voltage and return path. |
| 8 | 2Q̄ | output | Channel 2 inverted output; complement of Q output, driven by positive-edge clock or PRE/CLR inputs. |
| 9 | 2Q | output | Channel 2 output; direct flip-flop output, driven by positive-edge clock or PRE/CLR inputs. |
| 10 | 2PRE | input | Channel 2 preset input (active low); sets outputs regardless of other input levels when driven low. |
| 11 | 2CLK | input | Channel 2 positive-edge triggered clock input; positive-going edge triggers data transfer. |
| 12 | 2D | input | Channel 2 data input; transferred to outputs on positive-edge clock trigger when PRE and CLR are inactive. |
| 13 | 2CLR | input | Channel 2 clear input (active low); resets outputs regardless of other input levels when driven low. |
| 14 | VCC | power_in | Positive supply voltage; operating range 1.5 V to 5.5 V with balanced noise immunity at 30% of supply. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
CD74AC74M96 - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
cd74ac74m96-etched.step/cd74ac74m96-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd74ac74m96.step/cd74ac74m96.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (24 pp, sha256
128e3d2733904e14, retrieved 2026-10-01, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).