component

CD74AC74E

Public Made by Adom

by adom

Texas Instruments Flip Flops, PDIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic icscd74ac74efactory-2.0.0extractor-text

Verified CD74AC74E

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 14 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CD74AC74E · PDIP-14 · 14 pins
  • ✓copper: 14 copper pads, none touching another net
  • ✓datasheet: all 14 pin names found in the 18-page datasheet
  • ✓distributor: lcsc C1523205, digikey 296-32973-5-ND, mouser 595-CD74AC74E
  • ✓family: DIP-14_W7.62mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-din9f9km/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 14 pins = 14 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 14 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cd74ac74e.kicad_sym✓ cd74ac74e.kicad_mod✓ cd74ac74e.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers cd74ac74e: viewers · Ray
cd74ac74e-etched.glb Publish 0.1.0 · Ray
cd74ac74e-etched.step cd74ac74e: factory component page (tier=mfr) · Ray
cd74ac74e-hero.glb cd74ac74e: hero GLB from the etched model (keeps the MPN mark) · Ray
cd74ac74e-hero.overlay.json Publish 0.1.0 · Ray
cd74ac74e.glb Publish 0.1.0 · Ray
cd74ac74e.kicad_mod Publish 0.1.0 · Ray
cd74ac74e.kicad_sym Publish 0.1.0 · Ray
cd74ac74e.lbr Publish 0.1.0 · Ray
cd74ac74e.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier mfr, 14 pins · Ray

CD74AC74E

Texas Instruments · Flip Flops · PDIP-14

CD74AC74E from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1CLR input Active-low asynchronous clear for flip-flop 1; a low level resets the outputs regardless of the other inputs.
2 1D input Data input of flip-flop 1, transferred to the outputs on the positive-going clock edge when PRE and CLR are high.
3 1CLK input Positive-edge clock input of flip-flop 1; triggering occurs at a voltage level and is not directly related to clock rise time.
4 1PRE input Active-low asynchronous preset for flip-flop 1; a low level sets the outputs regardless of the other inputs.
5 1Q output True output of flip-flop 1 with ±24-mA drive at VCC = 4.5 V to 5.5 V.
6 1Q̄ output Complementary output of flip-flop 1 with ±24-mA drive at VCC = 4.5 V to 5.5 V.
7 GND power_in Ground; continuous current through VCC or GND is limited to ±100 mA.
8 2Q̄ output Complementary output of flip-flop 2 with ±24-mA drive at VCC = 4.5 V to 5.5 V.
9 2Q output True output of flip-flop 2 with ±24-mA drive at VCC = 4.5 V to 5.5 V.
10 2PRE input Active-low asynchronous preset for flip-flop 2; a low level sets the outputs regardless of the other inputs.
11 2CLK input Positive-edge clock input of flip-flop 2; triggering occurs at a voltage level and is not directly related to clock rise time.
12 2D input Data input of flip-flop 2, transferred to the outputs on the positive-going clock edge when PRE and CLR are high.
13 2CLR input Active-low asynchronous clear for flip-flop 2; a low level resets the outputs regardless of the other inputs.
14 VCC power_in Supply voltage, recommended 1.5 V to 5.5 V, absolute maximum -0.5 V to 6 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-14
Category Logic ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range VCC -0.5 6 V 2
Input clamp current IIK -20 20 mA VI < 0 or VI > VCC 2
Output clamp current IOK -50 50 mA VO < 0 or VO > VCC 2
Continuous output current IO -50 50 mA VO = 0 to VCC 2
Continuous current through VCC or GND -100 100 mA 2
Package thermal impedance, E package θJA 80 °C/W E package, JESD 51-7 2
Storage temperature range Tstg -65 150 °C 2
Supply voltage VCC 1.5 5.5 V -55°C to 125°C 3
High-level input voltage VIH 1.2 V VCC = 1.5 V, -55°C to 125°C 3
High-level input voltage VIH 2.1 V VCC = 3 V, -55°C to 125°C 3
High-level input voltage VIH 3.85 V VCC = 5.5 V, -55°C to 125°C 3
Low-level input voltage VIL 0.3 V VCC = 1.5 V, -55°C to 125°C 3
Low-level input voltage VIL 0.9 V VCC = 3 V, -55°C to 125°C 3
Low-level input voltage VIL 1.65 V VCC = 5.5 V, -55°C to 125°C 3
High-level output current IOH -24 mA VCC = 4.5 V to 5.5 V 3
Low-level output current IOL 24 mA VCC = 4.5 V to 5.5 V 3
Input transition rise or fall rate Δt/Δv 50 ns/V VCC = 1.5 V to 3 V 3
Input transition rise or fall rate Δt/Δv 20 ns/V VCC = 3.6 V to 5.5 V 3
High-level output voltage VOH 1.4 V VI = VIH or VIL, VCC = 1.5 V, -55°C to 125°C 3
High-level output voltage VOH 2.9 V IOH = -50 µA, VCC = 3 V, -55°C to 125°C 3
High-level output voltage VOH 4.4 V IOH = -50 µA, VCC = 4.5 V, -55°C to 125°C 3
High-level output voltage VOH 2.4 V IOH = -4 mA, VCC = 3 V, -55°C to 125°C 3
High-level output voltage VOH 3.7 V IOH = -24 mA, VCC = 4.5 V, -55°C to 125°C 3
Low-level output voltage VOL 0.1 V VI = VIH or VIL, VCC = 1.5 V, -55°C to 125°C 3
Low-level output voltage VOL 0.5 V IOL = 12 mA, VCC = 3 V, -55°C to 125°C 3
Input leakage current II -1 1 µA VI = VCC or GND, VCC = 5.5 V, -55°C to 125°C 3
Supply current ICC 80 µA VI = VCC or GND, IO = 0, VCC = 5.5 V, -55°C to 125°C 3
Input capacitance Ci 10 pF -55°C to 125°C 3
Clock frequency fclock 79 MHz VCC = 3.3 V ± 0.3 V, -55°C to 125°C 4
Pulse duration, PRE or CLR low tw 5.6 ns VCC = 3.3 V ± 0.3 V, -55°C to 125°C 4
Pulse duration, CLK tw 6.3 ns VCC = 3.3 V ± 0.3 V, -55°C to 125°C 4
Setup time, Data tsu 4.9 ns VCC = 3.3 V ± 0.3 V, -55°C to 125°C 4
Hold time, Data after CLK↑ th 0 ns VCC = 3.3 V ± 0.3 V, -55°C to 125°C 4
Recovery time, CLR↑ or PRE↑ before CLK↑ trec 4.7 ns VCC = 3.3 V ± 0.3 V, -55°C to 125°C 4
Clock frequency fclock 110 MHz VCC = 5 V ± 0.5 V, -55°C to 125°C 4
Pulse duration, PRE or CLR low tw 4 ns VCC = 5 V ± 0.5 V, -55°C to 125°C 4
Pulse duration, CLK tw 4.5 ns VCC = 5 V ± 0.5 V, -55°C to 125°C 4
Setup time, Data tsu 3.5 ns VCC = 5 V ± 0.5 V, -55°C to 125°C 4
Recovery time, CLR↑ or PRE↑ before CLK↑ trec 2.7 ns VCC = 5 V ± 0.5 V, -55°C to 125°C 4
Maximum clock frequency fmax 79 MHz VCC = 3.3 V ± 0.3 V, CL = 50 pF, -55°C to 125°C 5
Propagation delay CLK to Q or Q̅ (low-to-high) tPLH 3.5 14 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF, -55°C to 125°C 5
Propagation delay CLK to Q or Q̅ (high-to-low) tPHL 3.5 14 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF, -55°C to 125°C 5
Propagation delay PRE or CLR to Q or Q̅ (low-to-high) tPLH 3.7 14.7 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF, -55°C to 125°C 5
Propagation delay PRE or CLR to Q or Q̅ (high-to-low) tPHL 4 16.1 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF, -55°C to 125°C 5
Maximum clock frequency fmax 110 MHz VCC = 5 V ± 0.5 V, CL = 50 pF, -55°C to 125°C 5
Propagation delay CLK to Q or Q̅ (low-to-high) tPLH 2.5 10 ns VCC = 5 V ± 0.5 V, CL = 50 pF, -55°C to 125°C 5
Propagation delay CLK to Q or Q̅ (high-to-low) tPHL 2.5 10 ns VCC = 5 V ± 0.5 V, CL = 50 pF, -55°C to 125°C 5
Propagation delay PRE or CLR to Q or Q̅ (low-to-high) tPLH 2.6 10.5 ns VCC = 5 V ± 0.5 V, CL = 50 pF, -55°C to 125°C 5
Propagation delay PRE or CLR to Q or Q̅ (high-to-low) tPHL 2.9 11.5 ns VCC = 5 V ± 0.5 V, CL = 50 pF, -55°C to 125°C 5
Power dissipation capacitance Cpd 55 pF TA = 25°C 5

CAD (KiCad official)

  • Symbol: CD74AC74E
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: PDIP-14 (KiCad packages3D, STEP)
  • 3D model files: cd74ac74e-etched.step / cd74ac74e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74ac74e.step / cd74ac74e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (18 pp, sha256 3ad07b7ab9a14041, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF