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CD74AC299M96

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Texas Instruments Shift Registers, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD74AC299M96

Texas Instruments · Shift Registers · SOIC-20-300mil

CD74AC299M96 from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S0 input Mode-select input that, together with S1, selects hold, shift-right, shift-left or parallel-load operation, sampled on the rising edge of CP.
2 !OE1 input Active-low output enable; with OE2 and the mode inputs it controls whether the I/O terminals drive the register data, and a high level forces the I/O terminals off.
3 !OE2 input Active-low output enable for the I/O terminals; a high level on either OE1 or OE2 forces the I/O terminals into the high-impedance (off) state.
4 I/O6 tri_state Parallel data input/output terminal, a tri-state output combined with a CMOS buffered input.
5 I/O4 tri_state Parallel data input/output terminal, a tri-state output combined with a CMOS buffered input.
6 I/O2 tri_state Parallel data input/output terminal, a tri-state output combined with a CMOS buffered input.
7 I/O0 tri_state Parallel data input/output terminal, a tri-state output combined with a CMOS buffered input.
8 Q0 output Serial output of register stage 0, connected to the DS7 input of a preceding register when cascading.
9 !MR input Asynchronous active-low master reset for the 299 device; when low it clears the register regardless of the state of all other inputs.
10 GND power_in Ground reference for the device.
11 DS0 input Serial data input to register stage 0 (right-shift serial input), loaded on the rising edge of CP.
12 CP input Clock input; mode-select, serial and parallel data are loaded on the rising (low-to-high) edge of CP.
13 I/O1 tri_state Parallel data input/output terminal, a tri-state output combined with a CMOS buffered input.
14 I/O3 tri_state Parallel data input/output terminal, a tri-state output combined with a CMOS buffered input.
15 I/O5 tri_state Parallel data input/output terminal, a tri-state output combined with a CMOS buffered input.
16 I/O7 tri_state Parallel data input/output terminal, a tri-state output combined with a CMOS buffered input.
17 Q7 output Serial output of register stage 7, connected to the DS0 input of a following register when cascading.
18 DS7 input Serial data input to register stage 7 (left-shift serial input), loaded on the rising edge of CP.
19 S1 input Mode-select input that, together with S0, selects the register operating mode, sampled on the rising edge of CP.
20 VCC power_in Positive supply; the AC-type recommended supply range is 1.5 V to 5.5 V, with a 0.1 µF bypass capacitor recommended close to the pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20-300mil
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: CD74AC299M96
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: cd74ac299m96-etched.step / cd74ac299m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74ac299m96.step / cd74ac299m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 fbcafb13deed4fbf, retrieved 2026-10-10, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF