component

CD74AC273E

Public Made by Adom

by adom

Texas Instruments Flip Flops, PDIP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic icscd74ac273efactory-2.0.0extractor-text

Verified CD74AC273E

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 20 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CD74AC273E · PDIP-20 · 20 pins
  • ✓copper: 20 copper pads, none touching another net
  • ✓datasheet: all 20 pin names found in the 25-page datasheet
  • ✓distributor: lcsc C1550143, digikey 2156-CD74AC273E-ND, mouser 595-CD74AC273E
  • ✓family: DIP-20_W7.62mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-7ckzeqqg/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 20 pins = 20 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 20 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cd74ac273e.kicad_sym✓ cd74ac273e.kicad_mod✓ cd74ac273e.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 13h ago
viewers cd74ac273e: viewers · Ray 13h ago
cd74ac273e-etched.glb Publish 0.1.0 · Ray 13h ago
cd74ac273e-etched.step cd74ac273e: factory component page (tier=mfr) · Ray 13h ago
cd74ac273e-hero.glb cd74ac273e: hero GLB from the etched model (keeps the MPN mark) · Ray 13h ago
cd74ac273e-hero.overlay.json Publish 0.1.0 · Ray 13h ago
cd74ac273e.glb Publish 0.1.0 · Ray 13h ago
cd74ac273e.kicad_mod Publish 0.1.0 · Ray 13h ago
cd74ac273e.kicad_sym Publish 0.1.0 · Ray 13h ago
cd74ac273e.lbr Publish 0.1.0 · Ray 13h ago
cd74ac273e.step Publish 0.1.0 · Ray 13h ago
package.json Publish 0.1.0 · Ray 13h ago
page.json Set visibility: public · Ray 13h ago
README.md Publish 0.1.0 · Ray 13h ago
verification.json Verified: Published by the parts factory: tier mfr, 20 pins · Ray 13h ago

CD74AC273E

Texas Instruments · Flip Flops · PDIP-20

CD74AC273E from Texas Instruments, in a PDIP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MR input Active-low common reset; a low voltage level resets all eight flip-flops independent of the clock.
2 Q0 output Output of flip-flop 0, which takes the level of D0 on the positive-going clock edge.
3 D0 input Data input to flip-flop 0, transferred to Q0 on the positive-going edge of CP.
4 D1 input Data input to flip-flop 1, transferred to Q1 on the positive-going edge of CP.
5 Q1 output Output of flip-flop 1, which takes the level of D1 on the positive-going clock edge.
6 Q2 output Output of flip-flop 2, which takes the level of D2 on the positive-going clock edge.
7 D2 input Data input to flip-flop 2, transferred to Q2 on the positive-going edge of CP.
8 D3 input Data input to flip-flop 3, transferred to Q3 on the positive-going edge of CP.
9 Q3 output Output of flip-flop 3, which takes the level of D3 on the positive-going clock edge.
10 GND power_in Ground reference; all voltages in the datasheet are referenced to this pin.
11 CP input Common clock input; data at Dn is transferred to Qn on its positive-going edge.
12 Q4 output Output of flip-flop 4, which takes the level of D4 on the positive-going clock edge.
13 D4 input Data input to flip-flop 4, transferred to Q4 on the positive-going edge of CP.
14 D5 input Data input to flip-flop 5, transferred to Q5 on the positive-going edge of CP.
15 Q5 output Output of flip-flop 5, which takes the level of D5 on the positive-going clock edge.
16 Q6 output Output of flip-flop 6, which takes the level of D6 on the positive-going clock edge.
17 D6 input Data input to flip-flop 6, transferred to Q6 on the positive-going edge of CP.
18 D7 input Data input to flip-flop 7, transferred to Q7 on the positive-going edge of CP.
19 Q7 output Output of flip-flop 7, which takes the level of D7 on the positive-going clock edge.
20 VCC power_in Supply voltage; the AC types operate from 1.5V to 5.5V and the ACT types from 4.5V to 5.5V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-20
Category Logic ICs
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage VCC -0.5 6 V Absolute maximum rating 3
DC Input Diode Current IIK -20 20 mA For VI < -0.5V or VI > VCC + 0.5V 3
DC Output Diode Current IOK -50 50 mA For VO < -0.5V or VO > VCC + 0.5V 3
DC Output Source or Sink Current per Output Pin IO -50 50 mA For VO > -0.5V or VO < VCC + 0.5V 3
DC VCC or Ground Current ICC or IGND -100 100 mA Note 3 3
Maximum Junction Temperature (Plastic Package) TJ 150 oC Plastic package 3
Maximum Storage Temperature Range TSTG -65 150 oC 3
Maximum Lead Temperature (Soldering 10s) 300 oC Soldering 10s 3
Temperature Range TA -55 125 oC Operating conditions 3
Supply Voltage Range AC Types VCC 1.5 5.5 V AC Types (Note 4) 3
Input Rise and Fall Slew Rate AC Types 1.5V to 3V dt/dv 50 ns AC Types, 1.5V to 3V 3
Input Rise and Fall Slew Rate AC Types 3.6V to 5.5V dt/dv 20 ns AC Types, 3.6V to 5.5V 3
High Level Input Voltage VIH 1.2 V VCC=1.5V; -55oC to 125oC 3
High Level Input Voltage VIH 2.1 V VCC=3V; -55oC to 125oC 3
High Level Input Voltage VIH 3.85 V VCC=5.5V; -55oC to 125oC 3
Low Level Input Voltage VIL 0.3 V VCC=1.5V; -55oC to 125oC 3
Low Level Input Voltage VIL 0.9 V VCC=3V; -55oC to 125oC 3
Low Level Input Voltage VIL 1.65 V VCC=5.5V; -55oC to 125oC 3
High Level Output Voltage VOH 1.4 V VI=VIH or VIL; IO=-0.05mA; VCC=1.5V; -55oC to 125oC 3
High Level Output Voltage VOH 2.9 V VI=VIH or VIL; IO=-0.05mA; VCC=3V; -55oC to 125oC 3
High Level Output Voltage VOH 4.4 V VI=VIH or VIL; IO=-0.05mA; VCC=4.5V; -55oC to 125oC 3
High Level Output Voltage VOH 2.4 V VI=VIH or VIL; IO=-4mA; VCC=3V; -55oC to 125oC 3
High Level Output Voltage VOH 3.7 V VI=VIH or VIL; IO=-24mA; VCC=4.5V; -55oC to 125oC 3
High Level Output Voltage VOH 3.85 V VI=VIH or VIL; IO=-50mA (Note 6, 7); VCC=5.5V; -55oC to 125oC 3
Low Level Output Voltage VOL 0.1 V VI=VIH or VIL; IO=0.05mA; VCC=1.5V; -55oC to 125oC 4
Low Level Output Voltage VOL 0.5 V VI=VIH or VIL; IO=12mA; VCC=3V; -55oC to 125oC 4
Low Level Output Voltage VOL 1.65 V VI=VIH or VIL; IO=50mA (Note 6, 7); VCC=5.5V; -55oC to 125oC 4
Input Leakage Current II -1 1 µA VI=VCC or GND; VCC=5.5V; -55oC to 125oC 4
Quiescent Supply Current MSI ICC 160 µA VI=VCC or GND; VCC=5.5V; -55oC to 125oC 4
Prerequisite Data to CP Set-Up Time tSU 2 ns VCC=1.5V; -55oC to 125oC 5
Hold Time tH 2 ns VCC=1.5V; -55oC to 125oC 5
Removal Time, MR to CP tREM 2 ns VCC=1.5V; -55oC to 125oC 5
MR Pulse Width tW 63 ns VCC=1.5V; -55oC to 125oC 5
MR Pulse Width tW 7 ns VCC=3.3V; -55oC to 125oC 5
MR Pulse Width tW 5 ns VCC=5V; -55oC to 125oC 5
CP Pulse Width tW 63 ns VCC=1.5V; -55oC to 125oC 5
CP Pulse Width tW 7 ns VCC=3.3V; -55oC to 125oC 5
CP Pulse Width tW 5 ns VCC=5V; -55oC to 125oC 5
CP Frequency fMAX 8 MHz VCC=1.5V; -55oC to 125oC 5
CP Frequency fMAX 71 MHz VCC=3.3V; -55oC to 125oC 5
CP Frequency fMAX 100 MHz VCC=5V; -55oC to 125oC 5
Propagation Delay CP to Qn tPLH, tPHL 169 ns Input tr, tf = 3ns, CL = 50pF; VCC=1.5V; -55oC to 125oC 5
Propagation Delay CP to Qn tPLH, tPHL 4.7 18.9 ns Input tr, tf = 3ns, CL = 50pF; VCC=3.3V (Note 9); -55oC to 125oC 5
Propagation Delay CP to Qn tPLH, tPHL 3.4 13.5 ns Input tr, tf = 3ns, CL = 50pF; VCC=5V (Note 10); -55oC to 125oC 5
Propagation Delay MR to Qn tPLH, tPHL 169 ns Input tr, tf = 3ns, CL = 50pF; VCC=1.5V; -55oC to 125oC 6
Propagation Delay MR to Qn tPLH, tPHL 4.7 18.9 ns Input tr, tf = 3ns, CL = 50pF; VCC=3.3V; -55oC to 125oC 6
Propagation Delay MR to Qn tPLH, tPHL 3.4 13.5 ns Input tr, tf = 3ns, CL = 50pF; VCC=5V; -55oC to 125oC 6

CAD (KiCad official)

  • Symbol: CD74AC273E
  • Footprint: Package_DIP:DIP-20_W7.62mm
  • 3D model: PDIP-20 (KiCad packages3D, STEP)
  • 3D model files: cd74ac273e-etched.step / cd74ac273e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74ac273e.step / cd74ac273e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 5018ac9c7af730f1, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF