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CD74AC251M96

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Texas Instruments Logic ICs, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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CD74AC251M96

Texas Instruments · Logic ICs · SOIC-16

CD74AC251M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 I3 input Data input 3 is routed to the Y and Y outputs when S2 S1 S0 select it and OE is LOW.
2 I2 input Data input 2 is routed to the Y and Y outputs when S2 S1 S0 select it and OE is LOW.
3 I1 input Data input 1 is routed to the Y and Y outputs when S2 S1 S0 select it and OE is LOW.
4 I0 input Data input 0 is routed to the Y and Y outputs when S2 S1 S0 select it and OE is LOW.
5 Y output True multiplexer output that follows the selected data input when OE is LOW and goes high-impedance when OE is HIGH.
6 Y output Complement (inverted) multiplexer output that goes high-impedance when OE is HIGH.
7 OE input Output Enable; the device is enabled when OE is at a LOW logic level and both outputs are high-impedance when OE is HIGH.
8 GND power_in Ground reference for all voltages; the datasheet states all voltages are referenced to ground.
9 S2 input Input select 2, the most significant address bit that selects I4 through I7 when high.
10 S1 input Input select 1, the middle address bit that chooses among the data inputs within each group of four.
11 S0 input Input select 0, the least significant address bit that chooses between adjacent data inputs.
12 I7 input Data input 7, selected when S2 S1 S0 are all HIGH and OE is LOW.
13 I6 input Data input 6, selected when S2 and S1 are HIGH, S0 is LOW, and OE is LOW.
14 I5 input Data input 5, selected when S2 and S0 are HIGH, S1 is LOW, and OE is LOW.
15 I4 input Data input 4, selected when S2 is HIGH and S1 and S0 are LOW, with OE LOW.
16 VCC power_in Positive supply pin; the datasheet's recommended supply range is listed in Section 4.2 and the power supply can be any voltage between its MIN and MAX rating.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 1.5 V 4
Input or output voltage VI, VO 0 V 4
Input rise and fall slew rate dt/dv 50 ns AC types, 1.5V to 3V 4
Input rise and fall slew rate dt/dv 20 ns AC types, 3.6V to 5.5V 4
Temperature range TA -55 125 °C 4
Supply voltage VCC -0.5 6 V 4
Input diode current IIK -20 20 mA VI < -0.5V or VI > VCC + 0.5V 4
Output diode current IOK -50 50 mA VI < -0.5V or VI > VCC + 0.5V 4
Output source or sink current per output pin IO -50 50 mA VO < -0.5V or VO > VCC + 0.5V 4
VCC or ground current ICC/IGND -100 100 mA 4
Maximum junction temperature (plastic package) TJ 150 °C 4
Storage temperature Tstg -65 150 °C 4
Junction-to-ambient thermal resistance RθJA 119.9 °C/W D (SOIC) 16 pins 4
High level input voltage VIH 1.2 V VCC = 1.5 V, 25°C 4
High level input voltage VIH 2.1 V VCC = 3 V, 25°C 4
High level input voltage VIH 3.85 V VCC = 5.5 V, 25°C 4
Low level input voltage VIL 0.3 V VCC = 1.5 V, 25°C 4
Low level input voltage VIL 0.9 V VCC = 3 V, 25°C 4
Low level input voltage VIL 1.65 V VCC = 5.5 V, 25°C 4
High level output voltage VOH 1.4 V VIH or VIL, IO = -0.05 mA, VCC = 1.5 V, 25°C 5
High level output voltage VOH 2.9 V VIH or VIL, IO = -0.05 mA, VCC = 3 V, 25°C 5
High level output voltage VOH 4.4 V VIH or VIL, IO = -0.05 mA, VCC = 4.5 V, 25°C 5
High level output voltage VOH 2.58 V VIH or VIL, IO = -4 mA, VCC = 3 V, 25°C 5
High level output voltage VOH 3.94 V VIH or VIL, IO = -24 mA, VCC = 4.5 V, 25°C 5
High level output voltage VOH 2.48 V VIH or VIL, IO = -4 mA, VCC = 3 V, -40°C to 85°C 5
High level output voltage VOH 2.4 V VIH or VIL, IO = -4 mA, VCC = 3 V, -55°C to 125°C 5
High level output voltage VOH 3.8 V VIH or VIL, IO = -24 mA, VCC = 4.5 V, -40°C to 85°C 5
High level output voltage VOH 3.7 V VIH or VIL, IO = -24 mA, VCC = 4.5 V, -55°C to 125°C 5
High level output voltage VOH 3.85 V VIH or VIL, IO = -75 mA, VCC = 5.5 V, -40°C to 85°C (tested one output at a time, 1 s max) 5
Low level output voltage VOL 0.1 V VIH or VIL, IO = 0.05 mA, VCC = 1.5 V, 25°C 5
Low level output voltage VOL 0.36 V VIH or VIL, IO = 12 mA, VCC = 3 V, 25°C 5
Low level output voltage VOL 0.44 V VIH or VIL, IO = 12 mA, VCC = 3 V, -40°C to 85°C 5
Low level output voltage VOL 1.65 V VIH or VIL, IO = 75 mA, VCC = 5.5 V, -40°C to 85°C (tested one output at a time, 1 s max) 5
Low level output voltage VOL 0.5 V VIH or VIL, IO = 12 mA, VCC = 3 V, -55°C to 125°C 5
Input leakage current II -0.1 0.1 μA VCC or GND, VCC = 5.5 V, 25°C 5
Three-state leakage current IOZ -0.5 0.5 μA VIH or VIL, VO = VCC or GND, VCC = 5.5 V, 25°C 5
Quiescent supply current MSI ICC 8 μA VCC or GND, IO = 0, VCC = 5.5 V, 25°C 5
Quiescent supply current MSI ICC 80 μA VCC or GND, IO = 0, VCC = 5.5 V, -40°C to 85°C 5
Propagation delay, data to Y output tPLH, tPHL 153 ns VCC = 1.5 V, input tr, tf = 3ns, CL = 50pF, -40°C to 85°C 5
Propagation delay, data to Y output tPLH, tPHL 4.9 17.2 ns VCC = 3.3 V, input tr, tf = 3ns, CL = 50pF, -40°C to 85°C 5
Propagation delay, data to Y output tPLH, tPHL 3.5 12.3 ns VCC = 5 V, input tr, tf = 3ns, CL = 50pF, -40°C to 85°C 5
Propagation delay, data to Y-bar output tPLH, tPHL 169 ns VCC = 1.5 V, input tr, tf = 3ns, CL = 50pF, -40°C to 85°C 6
Propagation delay, select to Y output tPLH, tPHL 207 ns VCC = 1.5 V, input tr, tf = 3ns, CL = 50pF, -40°C to 85°C 6
Propagation delay, select to Y output tPLH, tPHL 6.6 23.2 ns VCC = 3.3 V, input tr, tf = 3ns, CL = 50pF, -40°C to 85°C 6
Propagation delay, select to Y output tPLH, tPHL 4.7 16.5 ns VCC = 5 V, input tr, tf = 3ns, CL = 50pF, -40°C to 85°C 6
Propagation delay, output enable and output disable to output tPZH, tPZL, tPHZ, tPLZ 155 ns VCC = 1.5 V, input tr, tf = 3ns, CL = 50pF, -40°C to 85°C 6
Propagation delay, output enable and output disable to output tPZH, tPZL, tPHZ, tPLZ 5.2 18.7 ns VCC = 3.3 V, input tr, tf = 3ns, CL = 50pF, -40°C to 85°C 6
Propagation delay, output enable and output disable to output tPZH, tPZL, tPHZ, tPLZ 3.5 12.3 ns VCC = 5 V, input tr, tf = 3ns, CL = 50pF, -40°C to 85°C 6
Three-state output capacitance CO 15 pF -40°C to 85°C 6
Input capacitance CI 10 pF -40°C to 85°C 6

CAD (KiCad official)

  • Symbol: CD74AC251M96
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: cd74ac251m96-etched.step / cd74ac251m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74ac251m96.step / cd74ac251m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (15 pp, sha256 d4d7ce7542a4855c, retrieved 2026-10-29, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF