# CD74AC20M96

**Texas Instruments** · Gates · SOIC-14

CD74AC20M96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Input A of NAND gate 1; unused inputs must be held at VCC or GND for proper operation. |
| 2 | 1B | input | Input B of NAND gate 1; unused inputs must be held at VCC or GND for proper operation. |
| 3 | NC | unconnected | No internal connection. |
| 4 | 1C | input | Input C of NAND gate 1; unused inputs must be held at VCC or GND for proper operation. |
| 5 | 1D | input | Input D of NAND gate 1; unused inputs must be held at VCC or GND for proper operation. |
| 6 | 1Y | output | Output of NAND gate 1, Y = A•B•C•D (positive logic), with ±24 mA output drive current. |
| 7 | GND | power_in | Ground reference for the device. |
| 8 | 2Y | output | Output of NAND gate 2, Y = A•B•C•D (positive logic), with ±24 mA output drive current. |
| 9 | 2A | input | Input A of NAND gate 2; unused inputs must be held at VCC or GND for proper operation. |
| 10 | 2B | input | Input B of NAND gate 2; unused inputs must be held at VCC or GND for proper operation. |
| 11 | NC | unconnected | No internal connection. |
| 12 | 2C | input | Input C of NAND gate 2; unused inputs must be held at VCC or GND for proper operation. |
| 13 | 2D | input | Input D of NAND gate 2; unused inputs must be held at VCC or GND for proper operation. |
| 14 | VCC | power_in | Supply voltage, 1.5 V to 5.5 V recommended operating range. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic ICs |
| Pins | 14 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 1.5 |  | 5.5 | V |  | 2 |
| High-level input voltage | VIH | 1.2 |  |  | V | VCC = 1.5 V | 2 |
| High-level input voltage | VIH | 2.1 |  |  | V | VCC = 3 V | 2 |
| High-level input voltage | VIH | 3.85 |  |  | V | VCC = 5.5 V | 2 |
| Low-level input voltage | VIL |  |  | 0.3 | V | VCC = 1.5 V | 2 |
| Low-level input voltage | VIL |  |  | 0.9 | V | VCC = 3 V | 2 |
| Low-level input voltage | VIL |  |  | 1.65 | V | VCC = 5.5 V | 2 |
| High-level output current | IOH | -24 |  |  | mA | VCC = 4.5 V to 5.5 V | 2 |
| Low-level output current | IOL |  |  | 24 | mA | VCC = 4.5 V to 5.5 V | 2 |
| Input transition rise or fall rate | dt/dv |  |  | 50 | ns/V | VCC = 1.5 V to 3 V | 2 |
| Input transition rise or fall rate | dt/dv |  |  | 20 | ns/V | VCC = 3.6 V to 5.5 V | 2 |
| Supply voltage range | VCC | -0.5 |  | 6 | V |  | 2 |
| Input clamp current | IIK | -20 |  | 20 | mA | VI < 0 or VI > VCC | 2 |
| Output clamp current | IOK | -50 |  | 50 | mA | VO < 0 or VO > VCC | 2 |
| Continuous output current | IO | -50 |  | 50 | mA | VO = 0 to VCC | 2 |
| Continuous current through VCC or GND |  | -100 |  | 100 | mA |  | 2 |
| Storage temperature range | Tstg | -65 |  | 150 | °C |  | 2 |
| Package thermal impedance, M package | θJA |  |  | 86 | °C/W | M package | 2 |
| High-level output voltage | VOH | 1.4 |  |  | V | VI = VIH or VIL; IOH = -50 µA; VCC = 1.5 V | 3 |
| High-level output voltage | VOH | 2.9 |  |  | V | VI = VIH or VIL; IOH = -50 µA; VCC = 3 V | 3 |
| High-level output voltage | VOH | 4.4 |  |  | V | VI = VIH or VIL; IOH = -50 µA; VCC = 4.5 V | 3 |
| High-level output voltage | VOH | 2.4 |  |  | V | VI = VIH or VIL; IOH = -4 mA; VCC = 3 V | 3 |
| High-level output voltage | VOH | 3.7 |  |  | V | VI = VIH or VIL; IOH = -24 mA; VCC = 4.5 V | 3 |
| High-level output voltage | VOH | 3.85 |  |  | V | VI = VIH or VIL; IOH = -50 mA; VCC = 5.5 V | 3 |
| Low-level output voltage | VOL |  |  | 0.1 | V | VI = VIH or VIL; IOL = 50 µA; VCC = 1.5 V | 3 |
| Low-level output voltage | VOL |  |  | 0.5 | V | VI = VIH or VIL; IOL = 12 mA; VCC = 3 V | 3 |
| Low-level output voltage | VOL |  |  | 1.65 | V | VI = VIH or VIL; IOL = 50 mA; VCC = 5.5 V | 3 |
| Input current | II | -1 |  | 1 | µA | VI = VCC or GND; VCC = 5.5 V | 3 |
| Supply current | ICC |  |  | 80 | µA | VI = VCC or GND, IO = 0; VCC = 5.5 V | 3 |
| Input capacitance | Ci |  | 10 |  | pF |  | 3 |
| Propagation delay tPLH/tPHL | tpd |  |  | 153 | ns | VCC = 1.5 V, CL = 50 pF | 3 |
| Propagation delay tPLH/tPHL | tpd | 4.3 |  | 17.1 | ns | VCC = 3.3 V ± 0.3 V, CL = 50 pF | 3 |
| Propagation delay tPLH/tPHL | tpd | 3.1 |  | 12.2 | ns | VCC = 5 V ± 0.5 V, CL = 50 pF | 4 |
| Power dissipation capacitance | Cpd |  | 48 |  | pF | TA = 25°C | 4 |

## CAD (KiCad official)

- Symbol: `CD74AC20M96`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files: `cd74ac20m96-etched.step` / `cd74ac20m96-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74ac20m96.step` / `cd74ac20m96.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd74ac20) (15 pp, sha256 `ea1a75810c4055a8`, retrieved 2026-11-02, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cd74ac20m96-datasheet.pdf)