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CD74AC175M96

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Texas Instruments Flip Flops, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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CD74AC175M96

Texas Instruments · Flip Flops · SOIC-16

CD74AC175M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLR input Direct clear input; when low it forces Q low and Q̅ high regardless of CLK or D, and CLR must be released (recovery time trec of 1 ns minimum before CLK↑) before the next clock edge.
2 1Q output True output of flip-flop 1, which follows D on the positive-going CLK edge and is held when CLK is high or low.
3 1Q̅ output Complementary output of flip-flop 1, always the inverse of 1Q.
4 1D input Data input of flip-flop 1; must meet the setup time (2 ns minimum) before CLK↑ and the hold time (2 ns minimum) after CLK↑.
5 2D input Data input of flip-flop 2; must meet the setup time (2 ns minimum) before CLK↑ and the hold time (2 ns minimum) after CLK↑.
6 2Q output True output of flip-flop 2, which follows D on the positive-going CLK edge and is held when CLK is high or low.
7 2Q output Complementary output of flip-flop 2, always the inverse of 2Q.
8 GND power_in Ground reference pin.
9 CLK input Common clock input for all four flip-flops; data transfers to the outputs on the positive-going edge, and the maximum clock frequency is 8 MHz at VCC = 1.5 V and 100 MHz at VCC = 5 V.
10 3Q output Complementary output of flip-flop 3, always the inverse of 3Q.
11 3Q output True output of flip-flop 3, which follows D on the positive-going CLK edge and is held when CLK is high or low.
12 3D input Data input of flip-flop 3; must meet the setup time (2 ns minimum) before CLK↑ and the hold time (2 ns minimum) after CLK↑.
13 4D input Data input of flip-flop 4; must meet the setup time (2 ns minimum) before CLK↑ and the hold time (2 ns minimum) after CLK↑.
14 4Q̅ output Complementary output of flip-flop 4, always the inverse of 4Q.
15 4Q output True output of flip-flop 4, which follows D on the positive-going CLK edge and is held when CLK is high or low.
16 VCC power_in Supply voltage, recommended 1.5 V to 5.5 V; absolute maximum rating is -0.5 V to 6 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 1.5 5.5 V TA = -55°C to 125°C 2
High-level input voltage VIH 1.2 V VCC = 1.5 V 2
High-level input voltage VIH 2.1 V VCC = 3 V 2
High-level input voltage VIH 3.85 V VCC = 5.5 V 2
Low-level input voltage VIL 0.3 V VCC = 1.5 V 2
Low-level input voltage VIL 0.9 V VCC = 3 V 2
Low-level input voltage VIL 1.65 V VCC = 5.5 V 2
Input voltage VI 0 V max = VCC 2
Output voltage VO 0 V max = VCC 2
High-level output current IOH -24 mA VCC = 4.5 V to 5.5 V 2
Low-level output current IOL 24 mA VCC = 4.5 V to 5.5 V 2
Input transition rise or fall rate Δt/Δv 50 ns/V VCC = 1.5 V to 3 V 2
Input transition rise or fall rate Δt/Δv 20 ns/V VCC = 3.6 V to 5.5 V 2
High-level output voltage VOH 1.4 V VI = VIH or VIL; IOH = -50 µA; VCC = 1.5 V 3
High-level output voltage VOH 2.9 V VI = VIH or VIL; IOH = -50 µA; VCC = 3 V 3
High-level output voltage VOH 4.4 V VI = VIH or VIL; IOH = -50 µA; VCC = 4.5 V 3
High-level output voltage VOH 2.4 V VI = VIH or VIL; IOH = -4 mA; VCC = 3 V 3
High-level output voltage VOH 3.7 V VI = VIH or VIL; IOH = -24 mA; VCC = 4.5 V 3
Low-level output voltage VOL 0.1 V VI = VIH or VIL; IOL = 50 µA; VCC = 1.5 V 3
Low-level output voltage VOL 0.5 V VI = VIH or VIL; IOL = 12 mA; VCC = 3 V 3
Input leakage current II -1 1 µA VI = VCC or GND; VCC = 5.5 V 3
Quiescent supply current ICC 160 µA VI = VCC or GND, IO = 0; VCC = 5.5 V 3
Clock frequency fclock 8 MHz VCC = 1.5 V 3
Pulse duration CLR low tw 50 ns VCC = 1.5 V; CLR low 3
Pulse duration CLK high or low tw 63 ns VCC = 1.5 V; CLK high or low 3
Setup time before CLK↑ (Data) tsu 2 ns VCC = 1.5 V 3
Hold time, data after CLK↑ th 2 ns VCC = 1.5 V 3
Recovery time, before CLK↑ (CLR↑) trec 1 ns VCC = 1.5 V 3
Clock frequency fclock 71 MHz VCC = 3.3 V ± 0.3 V 4
Pulse duration CLR low tw 5.6 ns VCC = 3.3 V ± 0.3 V; CLR low 4
Pulse duration CLK high or low tw 7 ns VCC = 3.3 V ± 0.3 V; CLK high or low 4
Setup time before CLK↑ (Data) tsu 2 ns VCC = 3.3 V ± 0.3 V 4
Hold time, data after CLK↑ th 2 ns VCC = 3.3 V ± 0.3 V 4
Recovery time, before CLK↑ (CLR↑) trec 1 ns VCC = 3.3 V ± 0.3 V 4
Clock frequency fclock 100 MHz VCC = 5 V ± 0.5 V 4
Pulse duration CLR low tw 4 ns VCC = 5 V ± 0.5 V; CLR low 4
Pulse duration CLK high or low tw 5 ns VCC = 5 V ± 0.5 V; CLK high or low 4
Maximum clock frequency fmax 8 MHz VCC = 1.5 V, CL = 50 pF 4
Propagation delay CLK to any Q tPLH/tPHL 153 ns VCC = 1.5 V, CL = 50 pF 4
Propagation delay CLR to any Q tPLH/tPHL 153 ns VCC = 1.5 V, CL = 50 pF 4
Maximum clock frequency fmax 71 MHz VCC = 3.3 V ± 0.3 V, CL = 50 pF 4
Propagation delay CLK to any Q tPLH/tPHL 4.3 17.1 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF 4
Propagation delay CLR to any Q tPLH/tPHL 4.3 17.1 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF 4
Maximum clock frequency fmax 100 MHz VCC = 5 V ± 0.5 V, CL = 50 pF 5
Propagation delay CLK to any Q tPLH/tPHL 3.1 12.2 ns VCC = 5 V ± 0.5 V, CL = 50 pF 5
Propagation delay CLR to any Q tPLH/tPHL 3.1 12.2 ns VCC = 5 V ± 0.5 V, CL = 50 pF 5
Supply voltage range VCC -0.5 6 V 2
Input clamp current IIK -20 20 mA VI < 0 V or VI > VCC (see Note 1) 2
Output clamp current IOK -50 50 mA VO < 0 V or VO > VCC (see Note 1) 2
Continuous output current IO -50 50 mA VO > 0 V or VO < VCC 2
Continuous current through VCC or GND -200 200 mA 2
Storage temperature range Tstg -65 150 °C 2
Package thermal impedance θJA 73 °C/W see Note 2 2

CAD (KiCad official)

  • Symbol: CD74AC175M96
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: cd74ac175m96-etched.step / cd74ac175m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74ac175m96.step / cd74ac175m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (13 pp, sha256 8e3fccde494e18e3, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF