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CD74AC174M96

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Texas Instruments Flip Flops, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD74AC174M96

Texas Instruments · Flip Flops · SOIC-16

CD74AC174M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLR input Active-low direct clear input: driving CLR low forces all Q outputs low regardless of CLK and D, and CLR must return high at least 1.5 ns before CLK rises (recovery time trec).
2 1Q output Output of flip-flop 1, which takes the value of 1D on the positive CLK edge and holds its state while CLR is high and CLK is not rising.
3 1D input Data input of flip-flop 1, which must be stable for the 2 ns setup time before the positive-going CLK edge.
4 2D input Data input of flip-flop 2, which must be stable for the 2 ns setup time before the positive-going CLK edge.
5 2Q output Output of flip-flop 2, which takes the value of 2D on the positive CLK edge and holds its state while CLR is high and CLK is not rising.
6 3D input Data input of flip-flop 3, which must be stable for the 2 ns setup time before the positive-going CLK edge.
7 3Q output Output of flip-flop 3, which takes the value of 3D on the positive CLK edge and holds its state while CLR is high and CLK is not rising.
8 GND power_in Ground pin.
9 CLK input Common clock input: D is transferred to Q on the positive-going CLK edge, and D has no effect at the output while CLK is high or low.
10 4Q output Output of flip-flop 4, which takes the value of 4D on the positive CLK edge and holds its state while CLR is high and CLK is not rising.
11 4D input Data input of flip-flop 4, which must be stable for the 2 ns setup time before the positive-going CLK edge.
12 5Q output Output of flip-flop 5, which takes the value of 5D on the positive CLK edge and holds its state while CLR is high and CLK is not rising.
13 5D input Data input of flip-flop 5, which must be stable for the 2 ns setup time before the positive-going CLK edge.
14 6D input Data input of flip-flop 6, which must be stable for the 2 ns setup time before the positive-going CLK edge.
15 6Q output Output of flip-flop 6, which takes the value of 6D on the positive CLK edge and holds its state while CLR is high and CLK is not rising.
16 VCC power_in Supply pin; the recommended supply range is 1.5 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: CD74AC174M96
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: cd74ac174m96-etched.step / cd74ac174m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74ac174m96.step / cd74ac174m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (27 pp, sha256 5adfeccb2ad3a5af, retrieved 2026-10-10, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF