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cd74ac164m96-etched.step	cd74ac164m96: factory component page (tier=lcsc) · Ray	2d ago
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README.md	Initial commit: component/cd74ac164m96 · Ray	2d ago

CD74AC164M96

Texas Instruments · Shift Registers · SOIC-14

CD74AC164M96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	A	input	Gated serial data input A; it is ANDed with input B, so both A and B must be high to set the first register high, and a low on either one sets it low.
2	B	input	Gated serial data input B; it is ANDed with input A, and data on A and B may change while CLK is high or low provided the minimum setup time is met.
3	QA	output	Parallel output QA from the first shift register stage, which takes the A·B result on each rising CLK edge.
4	QB	output	Parallel output QB from the second shift register stage, which receives the data of QA on each rising CLK edge.
5	QC	output	Parallel output QC from the third shift register stage, which receives the data of QB on each rising CLK edge.
6	QD	output	Parallel output QD from the fourth shift register stage, which receives the data of QC on each rising CLK edge.
7	GND	power_in	Ground reference for the device; the datasheet states that all voltages are referenced to ground.
8	CLK	input	Clock input that is rising-edge triggered, shifting the register data one stage on each low-to-high transition.
9	CLR	input	Asynchronous active-low register clear input; a low level immediately sets all shift register stages to logic low regardless of CLK.
10	QE	output	Parallel output QE from the fifth shift register stage, which receives the data of QD on each rising CLK edge.
11	QF	output	Parallel output QF from the sixth shift register stage, which receives the data of QE on each rising CLK edge.
12	QG	output	Parallel output QG from the seventh shift register stage, which receives the data of QF on each rising CLK edge.
13	QH	output	Parallel output QH from the eighth and last shift register stage; its data is discarded on each clock edge, and unused outputs may be left floating but must not be tied directly to VCC or GND.
14	VCC	power_in	Positive supply pin; the AC type operates from 1.5 V to 5.5 V and the ACT type from 4.5 V to 5.5 V, with a 0.1 µF bypass capacitor recommended close to the pin.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-14
Category	Logic
Pins	14

CAD (KiCad official)

Symbol: CD74AC164M96
Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
3D model: SOIC-14 (KiCad packages3D, STEP)
3D model files: cd74ac164m96-etched.step / cd74ac164m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74ac164m96.step / cd74ac164m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (38 pp, sha256 0826429779fac174, retrieved 2026-10-08, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF