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CD74AC164M96
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Texas Instruments Shift Registers, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+51@@ -0,0 +1,51 @@+# CD74AC164M96++**Texas Instruments** · Shift Registers · SOIC-14++CD74AC164M96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | A | input | Gated serial data input A; it is ANDed with input B, so both A and B must be high to set the first register high, and a low on either one sets it low. |+| 2 | B | input | Gated serial data input B; it is ANDed with input A, and data on A and B may change while CLK is high or low provided the minimum setup time is met. |+| 3 | QA | output | Parallel output QA from the first shift register stage, which takes the A·B result on each rising CLK edge. |+| 4 | QB | output | Parallel output QB from the second shift register stage, which receives the data of QA on each rising CLK edge. |+| 5 | QC | output | Parallel output QC from the third shift register stage, which receives the data of QB on each rising CLK edge. |+| 6 | QD | output | Parallel output QD from the fourth shift register stage, which receives the data of QC on each rising CLK edge. |+| 7 | GND | power_in | Ground reference for the device; the datasheet states that all voltages are referenced to ground. |+| 8 | CLK | input | Clock input that is rising-edge triggered, shifting the register data one stage on each low-to-high transition. |+| 9 | CLR | input | Asynchronous active-low register clear input; a low level immediately sets all shift register stages to logic low regardless of CLK. |+| 10 | QE | output | Parallel output QE from the fifth shift register stage, which receives the data of QD on each rising CLK edge. |+| 11 | QF | output | Parallel output QF from the sixth shift register stage, which receives the data of QE on each rising CLK edge. |+| 12 | QG | output | Parallel output QG from the seventh shift register stage, which receives the data of QF on each rising CLK edge. |+| 13 | QH | output | Parallel output QH from the eighth and last shift register stage; its data is discarded on each clock edge, and unused outputs may be left floating but must not be tied directly to VCC or GND. |+| 14 | VCC | power_in | Positive supply pin; the AC type operates from 1.5 V to 5.5 V and the ACT type from 4.5 V to 5.5 V, with a 0.1 µF bypass capacitor recommended close to the pin. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-14 |+| Category | Logic |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `CD74AC164M96`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOIC-14 (KiCad packages3D, STEP)+- 3D model files: `cd74ac164m96-etched.step` / `cd74ac164m96-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74ac164m96.step` / `cd74ac164m96.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd74ac164) (38 pp, sha256 `0826429779fac174`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd74ac164m96-datasheet.pdf)
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it is ANDed with input B, so both A and B must be high to set the first register high, and a low on either one sets it low."+ },+ {+ "number": "2",+ "name": "B",+ "type": "input",+ "description": "Gated serial data input B; it is ANDed with input A, and data on A and B may change while CLK is high or low provided the minimum setup time is met."+ },+ {+ "number": "3",+ "name": "QA",+ "type": "output",+ "description": "Parallel output QA from the first shift register stage, which takes the A·B result on each rising CLK edge."+ },+ {+ "number": "4",+ "name": "QB",+ "type": "output",+ "description": "Parallel output QB from the second shift register stage, which receives the data of QA on each rising CLK edge."+ },+ {+ "number": "5",+ "name": "QC",+ "type": "output",+ "description": "Parallel output QC from the third shift register stage, which receives the data of QB on each rising CLK edge."+ },+ {+ "number": "6",+ "name": "QD",+ "type": "output",+ "description": "Parallel output QD from the fourth shift register stage, which receives the data of QC on each rising CLK edge."+ },+ {+ "number": "7",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for the device; the datasheet states that all voltages are referenced to ground."+ },+ {+ "number": "8",+ "name": "CLK",+ "type": "input",+ "description": "Clock input that is rising-edge triggered, shifting the register data one stage on each low-to-high transition."+ },+ {+ "number": "9",+ "name": "CLR",+ "type": "input",+ "description": "Asynchronous active-low register clear input; a low level immediately sets all shift register stages to logic low regardless of CLK."+ },+ {+ "number": "10",+ "name": "QE",+ "type": "output",+ "description": "Parallel output QE from the fifth shift register stage, which receives the data of QD on each rising CLK edge."+ },+ {+ "number": "11",+ "name": "QF",+ "type": "output",+ "description": "Parallel output QF from the sixth shift register stage, which receives the data of QE on each rising CLK edge."+ },+ {+ "number": "12",+ "name": "QG",+ "type": "output",+ "description": "Parallel output QG from the seventh shift register stage, which receives the data of QF on each rising CLK edge."+ },+ {+ "number": "13",+ "name": "QH",+ "type": "output",+ "description": "Parallel output QH from the eighth and last shift register stage; its data is discarded on each clock edge, and unused outputs may be left floating but must not be tied directly to VCC or GND."+ },+ {+ "number": "14",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply pin; the AC type operates from 1.5 V to 5.5 V and the ACT type from 4.5 V to 5.5 V, with a 0.1 µF bypass capacitor recommended close to the pin."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The schema has no spec field, so the headline electrical specs (supply range, ICC, temperature) were"+ ],+ "pages_sent": 38,+ "cost_usd": 0.1246,+ "at": "2026-10-08T02:41:32"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/cd74ac164",+ "pages": 38,+ "sha256": "0826429779fac174",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "cd74ac164m96.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 8.7,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "cd74ac164m96-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 8.7,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "e226a8801fcd101981fcf6fbc88e949eb3965cb7c1244851d9b9a63d1b333a13",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}