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docs cd74ac163m96: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
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cd74ac163m96-etched.fit.json cd74ac163m96: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd74ac163m96-etched.glb cd74ac163m96: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd74ac163m96-etched.step cd74ac163m96: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd74ac163m96.glb Publish 0.1.0 · Ray
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README.md Initial commit: component/cd74ac163m96 · Ray

CD74AC163M96

Texas Instruments · Counters, Dividers · SOIC-16

CD74AC163M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLR input Synchronous clear input; a low level sets all four flip-flop outputs low after the next low-to-high transition of CLK.
2 CLK input Buffered clock input; triggers the four flip-flops on the rising (positive-going) edge of the clock waveform.
3 A input Parallel load/preset data input A; one of four inputs for presetting the counter to any number between 0 and 15.
4 B input Parallel load/preset data input B; one of four inputs for presetting the counter to any number between 0 and 15.
5 C input Parallel load/preset data input C; one of four inputs for presetting the counter to any number between 0 and 15.
6 D input Parallel load/preset data input D; one of four inputs for presetting the counter to any number between 0 and 15.
7 ENP input Count enable input (Enable P); both ENP and ENT must be high to enable counting.
8 GND power_in Ground; power return.
9 LOAD input Synchronous parallel load input; a low level disables the counter and causes outputs to agree with setup data after the next clock pulse.
10 ENT input Count enable input (Enable T/ripple carry enable); both ENP and ENT must be high to count; fed forward to enable RCO.
11 QD output Output QD; binary counter output D, the Q output of the D/T flip-flop for bit D.
12 QC output Output QC; binary counter output C, the Q output of the D/T flip-flop for bit C.
13 QB output Output QB; binary counter output B, the Q output of the D/T flip-flop for bit B.
14 QA output Output QA; binary counter output A, the Q output of the D/T flip-flop for bit A.
15 RCO output Ripple carry output; produces a high-level pulse while the count is at maximum (9 or 15 with QA high) and ENT is high, for cascading counters.
16 VCC power_in Positive supply voltage; operating range 1.5 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: CD74AC163M96
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: cd74ac163m96-etched.step / cd74ac163m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74ac163m96.step / cd74ac163m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (19 pp, sha256 052897f0e1e51344, retrieved 2026-09-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF