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CD74AC157M96

Public Made by Adom

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Texas Instruments Signal Switches, Multiplexers, Decoders, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD74AC157M96

Texas Instruments · Signal Switches, Multiplexers, Decoders · SOIC-16

CD74AC157M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A/B input Common select input: low selects the 1A, 2A, 3A and 4A sources and high selects the 1B, 2B, 3B and 4B sources, per the function table.
2 1A input Channel 1 data input from source A, routed to 1Y when A/B is low and G is low; unused inputs must be held at VCC or GND.
3 1B input Channel 1 data input from source B, routed to 1Y when A/B is high and G is low; unused inputs must be held at VCC or GND.
4 1Y output Channel 1 true data output, forced low when strobe G is high; drive capability is ±24 mA at 4.5 V to 5.5 V.
5 2A input Channel 2 data input from source A, routed to 2Y when A/B is low and G is low; unused inputs must be held at VCC or GND.
6 2B input Channel 2 data input from source B, routed to 2Y when A/B is high and G is low; unused inputs must be held at VCC or GND.
7 2Y output Channel 2 true data output, forced low when strobe G is high; drive capability is ±24 mA at 4.5 V to 5.5 V.
8 GND power_in Ground reference; continuous current through VCC or GND is limited to ±100 mA (absolute maximum).
9 3Y output Channel 3 true data output, forced low when strobe G is high; drive capability is ±24 mA at 4.5 V to 5.5 V.
10 3B input Channel 3 data input from source B, routed to 3Y when A/B is high and G is low; unused inputs must be held at VCC or GND.
11 3A input Channel 3 data input from source A, routed to 3Y when A/B is low and G is low; unused inputs must be held at VCC or GND.
12 4Y output Channel 4 true data output, forced low when strobe G is high; drive capability is ±24 mA at 4.5 V to 5.5 V.
13 4B input Channel 4 data input from source B, routed to 4Y when A/B is high and G is low; unused inputs must be held at VCC or GND.
14 4A input Channel 4 data input from source A, routed to 4Y when A/B is low and G is low; unused inputs must be held at VCC or GND.
15 G input Common active-low strobe: when high, all outputs are forced low; when low, the selected 4-bit word is routed to the outputs.
16 VCC power_in Supply voltage, 1.5 V to 5.5 V recommended operating range (absolute maximum 6 V).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 1.5 5.5 V TA = -55°C to 125°C 3
High-level input voltage VIH 1.2 V VCC = 1.5 V; TA = -55°C to 125°C 3
High-level input voltage VIH 2.1 V VCC = 3 V; TA = -55°C to 125°C 3
High-level input voltage VIH 3.85 V VCC = 5.5 V; TA = -55°C to 125°C 3
Low-level input voltage VIL 0.3 V VCC = 1.5 V; TA = -55°C to 125°C 3
Low-level input voltage VIL 0.9 V VCC = 3 V; TA = -55°C to 125°C 3
Low-level input voltage VIL 1.65 V VCC = 5.5 V; TA = -55°C to 125°C 3
Input voltage VI 0 V TA = -55°C to 125°C 3
Output voltage VO 0 V TA = -55°C to 125°C 3
High-level output current IOH -24 mA VCC = 4.5 V to 5.5 V; TA = -55°C to 125°C 3
Low-level output current IOL 24 mA VCC = 4.5 V to 5.5 V; TA = -55°C to 125°C 3
Input transition rise or fall rate Δt/Δv 50 ns/V VCC = 1.5 V to 3 V; TA = -55°C to 125°C 3
Input transition rise or fall rate Δt/Δv 20 ns/V VCC = 3.6 V to 5.5 V; TA = -55°C to 125°C 3
Supply voltage range VCC -0.5 6 V 2
Input clamp current IIK -20 20 mA VI < 0 V or VI > VCC (see Note 1) 2
Output clamp current IOK -50 50 mA VO < 0 V or VO > VCC (see Note 1) 2
Continuous output current IO -50 50 mA VO > 0 V or VO < VCC 2
Continuous current through VCC or GND -100 100 mA 2
Storage temperature range Tstg -65 150 °C 2
High-level output voltage VOH 1.4 V VI = VIH or VIL, IOH = -50 µA, VCC = 1.5 V; TA = -55°C to 125°C 3
High-level output voltage VOH 2.9 V VI = VIH or VIL, IOH = -50 µA, VCC = 3 V; TA = -55°C to 125°C 3
High-level output voltage VOH 4.4 V VI = VIH or VIL, IOH = -50 µA, VCC = 4.5 V; TA = -55°C to 125°C 3
High-level output voltage VOH 2.4 V VI = VIH or VIL, IOH = -4 mA, VCC = 3 V; TA = -55°C to 125°C 3
High-level output voltage VOH 3.7 V VI = VIH or VIL, IOH = -24 mA, VCC = 4.5 V; TA = -55°C to 125°C 3
Low-level output voltage VOL 0.1 V VI = VIH or VIL, IOL = 50 µA, VCC = 1.5 V; TA = -55°C to 125°C 3
Low-level output voltage VOL 0.5 V VI = VIH or VIL, IOL = 12 mA, VCC = 3 V; TA = -55°C to 125°C 3
Input leakage current II -1 1 µA VI = VCC or GND, VCC = 5.5 V; TA = -55°C to 125°C 3
Supply current ICC 160 µA VI = VCC or GND, IO = 0, VCC = 5.5 V; TA = -55°C to 125°C 3
Propagation delay, A or B to Y (low-to-high) tPLH 106 ns VCC = 1.5 V, CL = 50 pF; TA = -55°C to 125°C 4
Propagation delay, A or B to Y (high-to-low) tPHL 106 ns VCC = 1.5 V, CL = 50 pF; TA = -55°C to 125°C 4
Propagation delay, A/B to Y (low-to-high) tPLH 180 ns VCC = 1.5 V, CL = 50 pF; TA = -55°C to 125°C 4
Propagation delay, A/B to Y (high-to-low) tPHL 180 ns VCC = 1.5 V, CL = 50 pF; TA = -55°C to 125°C 4
Propagation delay, G to Y (low-to-high) tPLH 169 ns VCC = 1.5 V, CL = 50 pF; TA = -55°C to 125°C 4
Propagation delay, G to Y (high-to-low) tPHL 169 ns VCC = 1.5 V, CL = 50 pF; TA = -55°C to 125°C 4
Propagation delay, A or B to Y (low-to-high) tPLH 3 11.9 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF; TA = -55°C to 125°C 4
Propagation delay, A or B to Y (high-to-low) tPHL 3 11.9 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF; TA = -55°C to 125°C 4
Propagation delay, A/B to Y (low-to-high) tPLH 5.1 20.3 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF; TA = -55°C to 125°C 4
Propagation delay, A/B to Y (high-to-low) tPHL 5.1 20.3 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF; TA = -55°C to 125°C 4
Propagation delay, G to Y (low-to-high) tPLH 4.7 18.9 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF; TA = -55°C to 125°C 4
Propagation delay, G to Y (high-to-low) tPHL 4.7 18.9 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF; TA = -55°C to 125°C 4
Propagation delay, A or B to Y (low-to-high) tPLH 2.1 8.5 ns VCC = 5 V ± 0.5 V, CL = 50 pF; TA = -55°C to 125°C 4
Propagation delay, A or B to Y (high-to-low) tPHL 2.1 8.5 ns VCC = 5 V ± 0.5 V, CL = 50 pF; TA = -55°C to 125°C 4
Propagation delay, A/B to Y (low-to-high) tPLH 3.6 14.5 ns VCC = 5 V ± 0.5 V, CL = 50 pF; TA = -55°C to 125°C 4
Propagation delay, A/B to Y (high-to-low) tPHL 3.6 14.5 ns VCC = 5 V ± 0.5 V, CL = 50 pF; TA = -55°C to 125°C 4
Propagation delay, G to Y (low-to-high) tPLH 3.4 13.5 ns VCC = 5 V ± 0.5 V, CL = 50 pF; TA = -55°C to 125°C 4
Propagation delay, G to Y (high-to-low) tPHL 3.4 13.5 ns VCC = 5 V ± 0.5 V, CL = 50 pF; TA = -55°C to 125°C 4
Package thermal impedance, M package (SOIC) θJA 73 °C/W Calculated per JESD 51-7 (see Note 2) 2

CAD (KiCad official)

  • Symbol: CD74AC157M96
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: cd74ac157m96-etched.step / cd74ac157m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74ac157m96.step / cd74ac157m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (15 pp, sha256 301427dd23d14786, retrieved 2026-10-21, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF