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CD74AC112M96

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by adom

Texas Instruments Flip Flops, SOIC-16. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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CD74AC112M96

Texas Instruments · Flip Flops · SOIC-16

CD74AC112M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1CLK input Negative-edge-triggered clock input for flip-flop 1 that transfers J-K data to outputs when PRE and CLR are inactive (high).
2 1K input K control input for flip-flop 1 used with J to determine flip-flop behavior on clock edge.
3 1J input J control input for flip-flop 1 used with K to determine flip-flop behavior on clock edge.
4 1PRE input Active-low preset input for flip-flop 1 that forces Q high regardless of other inputs; requires 31 ns recovery time before next clock edge at 1.5 V VCC.
5 1Q output Q output for flip-flop 1 that goes high when preset is activated or when J=1 and K=0 on clock edge; capable of ±24 mA output drive.
6 1Q̄ output Complementary Q output for flip-flop 1 that is the logic inverse of 1Q; capable of ±24 mA output drive.
7 2Q output Q output for flip-flop 2 that goes high when preset is activated or when J=1 and K=0 on clock edge; capable of ±24 mA output drive.
8 GND power_in Ground pin providing the negative supply rail and logic reference potential.
9 2Q̄ output Complementary Q output for flip-flop 2 that is the logic inverse of 2Q; capable of ±24 mA output drive.
10 2PRE input Active-low preset input for flip-flop 2 that forces Q high regardless of other inputs; requires 31 ns recovery time before next clock edge at 1.5 V VCC.
11 2J input J control input for flip-flop 2 used with K to determine flip-flop behavior on clock edge.
12 2K input K control input for flip-flop 2 used with J to determine flip-flop behavior on clock edge.
13 2CLK input Negative-edge-triggered clock input for flip-flop 2 that transfers J-K data to outputs when PRE and CLR are inactive (high).
14 2CLR input Active-low clear input for flip-flop 2 that forces Q low regardless of other inputs; requires 31 ns recovery time before next clock edge at 1.5 V VCC.
15 1CLR input Active-low clear input for flip-flop 1 that forces Q low regardless of other inputs; requires 31 ns recovery time before next clock edge at 1.5 V VCC.
16 VCC power_in Positive supply voltage pin; acceptable range is 1.5 V to 5.5 V for proper device operation.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: CD74AC112M96
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: cd74ac112m96-etched.step / cd74ac112m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74ac112m96.step / cd74ac112m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (15 pp, sha256 1aabaad24ba07bd8, retrieved 2026-09-29, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF