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CD74AC02M96

Texas Instruments · Gates · SOIC-14

CD74AC02M96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1Y output Gate 1 output, the NOR of 1A and 1B (Y = A + B inverted), with ±24mA drive at VCC 4.5V to 5.5V.
2 1A input Gate 1 input A; unused inputs must be tied to VCC or GND, and input voltage range is 0 to VCC.
3 1B input Gate 1 input B; unused inputs must be tied to VCC or GND, and input voltage range is 0 to VCC.
4 2Y output Gate 2 output, the NOR of 2A and 2B, with ±24mA drive at VCC 4.5V to 5.5V.
5 2A input Gate 2 input A; unused inputs must be tied to VCC or GND, and input voltage range is 0 to VCC.
6 2B input Gate 2 input B; unused inputs must be tied to VCC or GND, and input voltage range is 0 to VCC.
7 GND power_in Ground pin.
8 3A input Gate 3 input A; unused inputs must be tied to VCC or GND, and input voltage range is 0 to VCC.
9 3B input Gate 3 input B; unused inputs must be tied to VCC or GND, and input voltage range is 0 to VCC.
10 3Y output Gate 3 output, the NOR of 3A and 3B, with ±24mA drive at VCC 4.5V to 5.5V.
11 4A input Gate 4 input A; unused inputs must be tied to VCC or GND, and input voltage range is 0 to VCC.
12 4B input Gate 4 input B; unused inputs must be tied to VCC or GND, and input voltage range is 0 to VCC.
13 4Y output Gate 4 output, the NOR of 4A and 4B, with ±24mA drive at VCC 4.5V to 5.5V.
14 VCC power_in Power supply pin, operating range 1.5V to 5.5V (absolute maximum 6V), with a 0.1µF bypass capacitor recommended close to the pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Logic ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 6 V 4
Input clamp current IIK -20 20 mA VI < 0 or VI > VCC 4
Output clamp current IOK -50 50 mA VO < 0 or VO > VCC 4
Continuous output current IO -50 50 mA VO = 0 to VCC 4
Continuous current through VCC or GND -100 100 mA 4
Storage temperature Tstg -65 150 °C 4
ESD HBM V(ESD) -2000 2000 V Human-body model 4
Supply voltage VCC 1.5 5.5 V -55°C to 125°C 4
High-level input voltage VIH 1.2 V VCC = 1.5V 4
High-level input voltage VIH 2.1 V VCC = 3V 4
High-level input voltage VIH 3.85 V VCC = 5.5V 4
Low-level input voltage VIL 0.3 V VCC = 1.5V 4
Low-level input voltage VIL 0.9 V VCC = 3V 4
Low-level input voltage VIL 1.65 V VCC = 5.5V 4
Input voltage VI 0 5.5 V 0 to VCC 4
Output voltage VO 0 5.5 V 0 to VCC 4
High-level output current IOH -24 mA VCC = 4.5V to 5.5V 4
Low-level output current IOL 24 mA VCC = 4.5V to 5.5V 4
Input transition rise or fall rate Δt/Δv 50 ns/V VCC = 1.5V to 3V 4
Input transition rise or fall rate Δt/Δv 20 ns/V VCC = 3.6V to 5.5V 4
Junction-to-ambient thermal resistance (D SOIC 14) RθJA 119.9 °C/W D (SOIC), 14 pins 5
High-level output voltage VOH 1.4 V VI = VIH or VIL, IOH = -50µA, VCC = 1.5V, -55°C to 125°C 5
High-level output voltage VOH 2.9 V VI = VIH or VIL, IOH = -50µA, VCC = 3V, -55°C to 125°C 5
High-level output voltage VOH 4.4 V VI = VIH or VIL, IOH = -50µA, VCC = 4.5V, -55°C to 125°C 5
High-level output voltage VOH 2.4 V VI = VIH or VIL, IOH = -4mA, VCC = 3V, -55°C to 125°C 5
High-level output voltage VOH 3.7 V VI = VIH or VIL, IOH = -24mA, VCC = 4.5V, -55°C to 125°C 5
Low-level output voltage VOL 0.1 V VI = VIH or VIL, IOL = 50µA, VCC = 1.5V, -55°C to 125°C 5
Low-level output voltage VOL 0.5 V VI = VIH or VIL, IOL = 12mA, VCC = 3V, -55°C to 125°C 5
Input current II -1 1 μA VI = VCC or GND, VCC = 5.5V, -55°C to 125°C 5
Supply current ICC 80 μA VI = VCC or GND, IO = 0, VCC = 5.5V, -55°C to 125°C 5
Input capacitance Ci 10 pF 5
Propagation delay A or B to Y (tPLH) tPLH 144 ns VCC = 1.5V, CL = 50pF, -55°C to 125°C 5
Propagation delay A or B to Y (tPHL) tPHL 144 ns VCC = 1.5V, CL = 50pF, -55°C to 125°C 5
Propagation delay A or B to Y (tPLH) tPLH 4 16.1 ns VCC = 3.3V ± 0.3V, CL = 50pF, -55°C to 125°C 6
Propagation delay A or B to Y (tPHL) tPHL 4 16.1 ns VCC = 3.3V ± 0.3V, CL = 50pF, -55°C to 125°C 6
Propagation delay A or B to Y (tPLH) tPLH 2.9 11.5 ns VCC = 5V ± 0.5V, CL = 50pF, -55°C to 125°C 6
Propagation delay A or B to Y (tPHL) tPHL 2.9 11.5 ns VCC = 5V ± 0.5V, CL = 50pF, -55°C to 125°C 6
Power dissipation capacitance Cpd 55 pF VCC = 5V, TA = 25°C 6

CAD (KiCad official)

  • Symbol: CD74AC02M96
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: cd74ac02m96-etched.step / cd74ac02m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74ac02m96.step / cd74ac02m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (31 pp, sha256 971198522538d39e, retrieved 2026-10-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF