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CD5035IHTS
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Shenzhen CYT Semicon Tech DC-DC Converters, HTSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CD5035IHTS
Shenzhen CYT Semicon Tech · DC-DC Converters · HTSSOP-20
CD5035IHTS from Shenzhen CYT Semicon Tech, in a HTSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RAMP | input | Ramp modulation pin, where an external RC network on VIN sets the ramp slope, and an internal FET discharges it at the end of each cycle. |
| 2 | UVLO | input | Input undervoltage lockout pin, where an external divider sets the shutdown and standby levels; VCC and REF regulators enable at 0.4V, SS is released at the 1.25V threshold, and hysteresis is a 23µA current sink. |
| 3 | OVP | input | Input overvoltage protection pin, where an external divider sets the shutdown level against a 1.25V threshold, with 23µA hysteresis current supplied by an internal source. |
| 4 | COMP | input | Pulse-width adjust input, where optocoupler current feeds an internal NPN current mirror; duty cycle is maximum at zero input current and falls to zero at 1mA. |
| 5 | RT | input | Oscillator frequency control and sync clock input, typically biased at 2V; an external resistor from RT to AGND sets the free-running frequency, and external sync can run above that frequency. |
| 6 | AGND | power_in | Analog ground pin, connected directly to the power supply ground. |
| 7 | CS | input | Current sense input; the output pulse is terminated cycle by cycle when CS exceeds 0.25V, and CS is held low for 50ns after the leading-edge blanking time. |
| 8 | SS | passive | Soft-start input, where an internal 55µA source charges the external capacitor to set the soft-start rate, reduced to 1.2µA during current-limit restart sequences. |
| 9 | DLY | passive | Timing programming pin, where an external resistor to ground sets the non-overlap time between HO to SR1 and LO to SR2. |
| 10 | RES | passive | Restart timing pin, which receives 22µA into its capacitor on any cycle exceeding cycle-by-cycle current limit; at 2.5V the soft-start capacitor is fully discharged and then released with a 1.2µA pull-up. |
| 11 | HB | power_in | Bootstrap pin for the HO driver, requiring an external diode from VCC and an external capacitor from HS to supply the high-side gate driver. |
| 12 | HS | passive | Switch node, the common connection of the transformer and the two power switches, providing the return path for the HO gate driver. |
| 13 | HO | output | High-side PWM gate drive output, rated to sink 2A peak current. |
| 14 | LO | output | Low-side PWM gate drive output, rated to sink 2A peak current. |
| 15 | PGND | power_in | Power ground pin, connected directly to the analog ground. |
| 16 | VCC | power_in | High-voltage start-up regulator pin; the start regulator turns off when an auxiliary winding raises this pin above the setpoint, and the recommended VCC range is 8V to 15V. |
| 17 | SR2 | output | Synchronous rectifier drive output 2, controlling the sync FET gate with 0.5A peak current capability. |
| 18 | SR1 | output | Synchronous rectifier drive output 1, controlling the sync FET gate with 0.5A peak current capability. |
| 19 | REF | power_out | Reference voltage output with a maximum output current of 20mA, decoupled locally with a 0.1pF capacitor as printed in the datasheet. |
| 20 | VIN | power_in | Power input pin with an operating input range of 13V to 105V; supplies outside this range can be applied directly to VCC through an external regulator. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Shenzhen CYT Semicon Tech |
| Package | HTSSOP-20 |
| Category | Power Management (PMIC) |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 输入电压 (input voltage, VIN pin) | VIN | 13 | 105 | V | 3 | ||
| VCC 电压 | VCC | 8 | 15 | V | 3 | ||
| 工作温度 (operating temperature) | -40 | 125 | ℃ | 3 | |||
| VIN to GND | VIN | -0.3 | 105 | V | 3 | ||
| VCC to GND | VCC | -0.3 | 16 | V | 3 | ||
| RT to GND | RT | -0.3 | 5.5 | V | 3 | ||
| ALL other PIN to GND | -0.3 | 7 | V | 3 | |||
| VCC电压 | VVCC | 7.3 | 7.6 | 7.9 | V | IVCC=10mA | 4 |
| VCC带载能力 | IVCC-limit | 20 | 25 | mA | VVCC = 7 V | 4 | |
| VCC欠压阈值 | VVCCUV | 5.5 | 6.2 | 6.9 | V | VCC, PGND | 4 |
| REF电压 | VREF | 4.85 | 5 | 5.15 | V | IREF = 0 mA | 4 |
| REF电压调节 | VREF-REG | 25 | 50 | mV | IREF = 0 mA ~ 10 mA | 4 | |
| REF电流限制 | IREF-LIMIT | 15 | 20 | mA | REF = 4.5 V | 4 | |
| UVLO参考电压 | VUVLO | 1.212 | 1.25 | 1.288 | V | 4 | |
| UVLO关断时迟滞电流 | IUVLO | 19 | 23 | 27 | µA | 4 | |
| 软启动充电电流 | ISS | 40 | 55 | 70 | µA | VSS = 0V | 4 |
| 打嗝模式重启电流 | 0.6 | 1.2 | 1.8 | µA | VSS = 0V | 4 | |
| 软停止吸收电流 | 40 | 55 | 70 | µA | VSS = 2.5V | 4 | |
| 逐周期过流比较阈值 | VCS | 0.228 | 0.25 | 0.272 | V | 4 | |
| 脉冲频率1 | FOSC1 | 180 | 200 | 220 | kHz | RRT=15kΩ | 5 |
| 脉冲频率2 | FOSC2 | 430 | 500 | 570 | kHz | RRT=5.49kΩ | 5 |
| 输入外同步脉冲阈值 | VSYNC | 2.5 | 3 | 3.4 | V | 5 | |
| 输出脉冲最小占空比 | Duty(min) | 0 | % | SS=0V | 5 | ||
| SS到RAMP偏移 | VPWM-OS | 0.7 | 1 | 1.2 | V | 5 | |
| 输出低电平 (HO到LO driver) | VL1 | 0.2 | 0.5 | V | IOUT=100mA | 5 | |
| 死区时间 HO-LO, LO-HO | DT | 45 | 70 | 100 | ns | VDLY=VRE, ICOMP=0mA | 5 |
| RAMP比较器临界点 | VRAMP-th | 2.4 | 2.5 | 2.6 | V | COMP电流=0A | 5 |
| 死区时间 SR1下降到HO上升, SR2下降到LO上升 | DT1 | 75 | 86 | 125 | ns | RDLY= 27.4 kΩ | 5 |
CAD (KiCad official)
- Symbol:
CD5035IHTS - Footprint:
Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm - 3D model: HTSSOP-20, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
cd5035ihts-etched.step/cd5035ihts-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd5035ihts.step/cd5035ihts.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Shenzhen CYT Semicon Tech datasheet (13 pp, sha256
c542b47ea5017dae, retrieved 2026-10-19, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CD5035IHTS
**Shenzhen CYT Semicon Tech** · DC-DC Converters · HTSSOP-20
CD5035IHTS from Shenzhen CYT Semicon Tech, in a HTSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RAMP | input | Ramp modulation pin, where an external RC network on VIN sets the ramp slope, and an internal FET discharges it at the end of each cycle. |
| 2 | UVLO | input | Input undervoltage lockout pin, where an external divider sets the shutdown and standby levels; VCC and REF regulators enable at 0.4V, SS is released at the 1.25V threshold, and hysteresis is a 23µA current sink. |
| 3 | OVP | input | Input overvoltage protection pin, where an external divider sets the shutdown level against a 1.25V threshold, with 23µA hysteresis current supplied by an internal source. |
| 4 | COMP | input | Pulse-width adjust input, where optocoupler current feeds an internal NPN current mirror; duty cycle is maximum at zero input current and falls to zero at 1mA. |
| 5 | RT | input | Oscillator frequency control and sync clock input, typically biased at 2V; an external resistor from RT to AGND sets the free-running frequency, and external sync can run above that frequency. |
| 6 | AGND | power_in | Analog ground pin, connected directly to the power supply ground. |
| 7 | CS | input | Current sense input; the output pulse is terminated cycle by cycle when CS exceeds 0.25V, and CS is held low for 50ns after the leading-edge blanking time. |
| 8 | SS | passive | Soft-start input, where an internal 55µA source charges the external capacitor to set the soft-start rate, reduced to 1.2µA during current-limit restart sequences. |
| 9 | DLY | passive | Timing programming pin, where an external resistor to ground sets the non-overlap time between HO to SR1 and LO to SR2. |
| 10 | RES | passive | Restart timing pin, which receives 22µA into its capacitor on any cycle exceeding cycle-by-cycle current limit; at 2.5V the soft-start capacitor is fully discharged and then released with a 1.2µA pull-up. |
| 11 | HB | power_in | Bootstrap pin for the HO driver, requiring an external diode from VCC and an external capacitor from HS to supply the high-side gate driver. |
| 12 | HS | passive | Switch node, the common connection of the transformer and the two power switches, providing the return path for the HO gate driver. |
| 13 | HO | output | High-side PWM gate drive output, rated to sink 2A peak current. |
| 14 | LO | output | Low-side PWM gate drive output, rated to sink 2A peak current. |
| 15 | PGND | power_in | Power ground pin, connected directly to the analog ground. |
| 16 | VCC | power_in | High-voltage start-up regulator pin; the start regulator turns off when an auxiliary winding raises this pin above the setpoint, and the recommended VCC range is 8V to 15V. |
| 17 | SR2 | output | Synchronous rectifier drive output 2, controlling the sync FET gate with 0.5A peak current capability. |
| 18 | SR1 | output | Synchronous rectifier drive output 1, controlling the sync FET gate with 0.5A peak current capability. |
| 19 | REF | power_out | Reference voltage output with a maximum output current of 20mA, decoupled locally with a 0.1pF capacitor as printed in the datasheet. |
| 20 | VIN | power_in | Power input pin with an operating input range of 13V to 105V; supplies outside this range can be applied directly to VCC through an external regulator. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Shenzhen CYT Semicon Tech |
| Package | HTSSOP-20 |
| Category | Power Management (PMIC) |
| Pins | 21 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 输入电压 (input voltage, VIN pin) | VIN | 13 | | 105 | V | | 3 |
| VCC 电压 | VCC | 8 | | 15 | V | | 3 |
| 工作温度 (operating temperature) | | -40 | | 125 | ℃ | | 3 |
| VIN to GND | VIN | -0.3 | | 105 | V | | 3 |
| VCC to GND | VCC | -0.3 | | 16 | V | | 3 |
| RT to GND | RT | -0.3 | | 5.5 | V | | 3 |
| ALL other PIN to GND | | -0.3 | | 7 | V | | 3 |
| VCC电压 | VVCC | 7.3 | 7.6 | 7.9 | V | IVCC=10mA | 4 |
| VCC带载能力 | IVCC-limit | 20 | 25 | | mA | VVCC = 7 V | 4 |
| VCC欠压阈值 | VVCCUV | 5.5 | 6.2 | 6.9 | V | VCC, PGND | 4 |
| REF电压 | VREF | 4.85 | 5 | 5.15 | V | IREF = 0 mA | 4 |
| REF电压调节 | VREF-REG | | 25 | 50 | mV | IREF = 0 mA ~ 10 mA | 4 |
| REF电流限制 | IREF-LIMIT | 15 | 20 | | mA | REF = 4.5 V | 4 |
| UVLO参考电压 | VUVLO | 1.212 | 1.25 | 1.288 | V | | 4 |
| UVLO关断时迟滞电流 | IUVLO | 19 | 23 | 27 | µA | | 4 |
| 软启动充电电流 | ISS | 40 | 55 | 70 | µA | VSS = 0V | 4 |
| 打嗝模式重启电流 | | 0.6 | 1.2 | 1.8 | µA | VSS = 0V | 4 |
| 软停止吸收电流 | | 40 | 55 | 70 | µA | VSS = 2.5V | 4 |
| 逐周期过流比较阈值 | VCS | 0.228 | 0.25 | 0.272 | V | | 4 |
| 脉冲频率1 | FOSC1 | 180 | 200 | 220 | kHz | RRT=15kΩ | 5 |
| 脉冲频率2 | FOSC2 | 430 | 500 | 570 | kHz | RRT=5.49kΩ | 5 |
| 输入外同步脉冲阈值 | VSYNC | 2.5 | 3 | 3.4 | V | | 5 |
| 输出脉冲最小占空比 | Duty(min) | | | 0 | % | SS=0V | 5 |
| SS到RAMP偏移 | VPWM-OS | 0.7 | 1 | 1.2 | V | | 5 |
| 输出低电平 (HO到LO driver) | VL1 | | 0.2 | 0.5 | V | IOUT=100mA | 5 |
| 死区时间 HO-LO, LO-HO | DT | 45 | 70 | 100 | ns | VDLY=VRE, ICOMP=0mA | 5 |
| RAMP比较器临界点 | VRAMP-th | 2.4 | 2.5 | 2.6 | V | COMP电流=0A | 5 |
| 死区时间 SR1下降到HO上升, SR2下降到LO上升 | DT1 | 75 | 86 | 125 | ns | RDLY= 27.4 kΩ | 5 |
## CAD (KiCad official)
- Symbol: `CD5035IHTS`
- Footprint: `Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm`
- 3D model: HTSSOP-20, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `cd5035ihts-etched.step` / `cd5035ihts-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd5035ihts.step` / `cd5035ihts.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Shenzhen CYT Semicon Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590917178906521600) (13 pp, sha256 `c542b47ea5017dae`, retrieved 2026-10-19, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cd5035ihts-datasheet.pdf)