component
CD5021IVS
Public Made by Adomby adom
Shenzhen CYT Semicon Tech DC-DC Converters, VSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 17d ago |
| viewers | 17d ago |
| cd5021ivs-etched.glb | 17d ago |
| cd5021ivs-etched.step | 17d ago |
| cd5021ivs-hero.glb | 17d ago |
| cd5021ivs-hero.overlay.json | 17d ago |
| cd5021ivs.glb | 17d ago |
| cd5021ivs.kicad_mod | 17d ago |
| cd5021ivs.kicad_sym | 17d ago |
| cd5021ivs.lbr | 17d ago |
| cd5021ivs.step | 17d ago |
| package.json | 17d ago |
| page.json | 17d ago |
| README.md | 17d ago |
CD5021IVS
Shenzhen CYT Semicon Tech · DC-DC Converters · VSSOP-8
CD5021IVS from Shenzhen CYT Semicon Tech, in a VSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | bidirectional | PWM and hiccup-mode control node, internally pulled up through a 5 kΩ resistor for optocoupler transistor biasing, with open-circuit voltage 4.2-6.0 V and short-circuit current 0.6-1.5 mA. |
| 2 | VIN | power_in | Input for the start-up regulator, clamped internally to 36 V by a zener, with a recommended operating range of 8 V to 30 V and VIN of at least 20 V needed for the first start-up. |
| 3 | VCC | power_out | Linear regulator output, typically 8.5 V (8.0-9.0 V), that biases the controller and gate driver, must be bypassed with a capacitor to GND, and must not be driven by the auxiliary winding or an external supply. |
| 4 | OUT | output | MOSFET gate driver output with a maximum source (charge) current of 0.3 A and maximum sink (discharge) current of 0.7 A. |
| 5 | GND | power_in | Reference ground for the controller. |
| 6 | CS | input | Current-sense input for peak current mode control and cycle-by-cycle overcurrent protection, with a 0.45-0.55 V threshold, and CS must stay low for 90 ns after the OUT driver turns on to blank the leading-edge spike. |
| 7 | RT | bidirectional | Oscillator timing resistor pin set to GND (RT = 6.63×10^9 / FSW, RT in kΩ, FSW in kHz), which also accepts external clock sync pulses, with an absolute maximum of 5.5 V. |
| 8 | SS | passive | Soft-start and hiccup timing pin charged by an internal 22 µA source through an external capacitor, which sets the soft-start slope and hiccup period, with open-circuit voltage 4.3-6.1 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Shenzhen CYT Semicon Tech |
| Package | VSSOP-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC output voltage | VVCC | 8 | 8.5 | 9 | V | COMP=5V,CS=0V | 4 |
| VCC regulator enable threshold | VVIN-EN | 17 | 20 | 23 | V | 4 | |
| Start-up regulator leakage current | IVIN | 2.5 | 3.75 | mA | COMP=0V,CS=0V | 4 | |
| VCC load capability | IVCC-limit | 15 | 22 | mA | COMP=5V,CS=0V | 4 | |
| VCC UVLO rising threshold | VVCC-EN | 6.5 | 7.2 | 7.5 | V | VIN=7V,CS=0V | 4 |
| VCC UVLO falling threshold | VVCC-DIS | 5.1 | 5.8 | 6.3 | V | 4 | |
| Overcurrent protection threshold | VCS | 0.45 | 0.5 | 0.55 | V | 4 | |
| Soft-start charging current | ISS | 15 | 22 | 30 | μA | COMP=2V,CS=SS=0V | 4 |
| SS open-circuit voltage | VSS-OCV | 4.3 | 5 | 6.1 | V | COMP=2V,CSS=5nF | 4 |
| COMP open-circuit voltage | VCOMP | 4.2 | 4.78 | 6 | V | SS=4.5V,CSS=5nF | 4 |
| COMP short-circuit current | ICOMP | 0.6 | 0.95 | 1.5 | mA | COMP=0V,CS=0V | 4 |
| Pulse (switching) frequency | FOSC | 135 | 150 | 165 | kHz | COMP=2V,CS=0V | 4 |
| Maximum output duty cycle | Duty（max） | 75 | 80 | 85 | % | 4 | |
| VIN to GND | -0.3 | 30 | V | 3 | |||
| VCC to GND | -0.3 | 10 | V | 3 | |||
| CS to GND | -0.3 | 1.25 | V | 3 | |||
| RT to GND | -0.3 | 5.5 | V | 3 | |||
| All other pins to GND | -0.3 | 7 | V | 3 | |||
| Input voltage VIN | 8 | 30 | V | Footnote a: at first start-up VIN must be ≥20V to enter normal operation | 3 | ||
| VCC voltage | 8 | 10 | V | 3 | |||
| Operating temperature range | -40 | 125 | ℃ | 3 |
CAD (KiCad official)
- Symbol:
CD5021IVS - Footprint:
Package_SO:VSSOP-8_2.3x2mm_P0.5mm - 3D model: VSSOP-8 (KiCad packages3D, STEP)
- 3D model files:
cd5021ivs-etched.step/cd5021ivs-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd5021ivs.step/cd5021ivs.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Shenzhen CYT Semicon Tech datasheet (11 pp, sha256
50a42e2c245adec0, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).