component
CD4541BE
Public Made by Adomby adom
Texas Instruments Timers / Counters, DIP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD4541BE
Texas Instruments · Timers / Counters · DIP-14
CD4541BE from Texas Instruments, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RTC | passive | Timing resistor connection for RC oscillator per f=1/(2.3×RTC×CTC) with 2RTC≈CTC constraint, operating range 1kHz to 100kHz. |
| 2 | CTC | passive | Timing capacitor connection for RC oscillator per f=1/(2.3×RTC×CTC) with 2RTC≈CTC constraint, operating range 1kHz to 100kHz. |
| 3 | RS | input | Series resistor connection for RC oscillator (RS ≥ 10kΩ minimum) that alternatively accepts external clock input DC to 100kHz instead of internal oscillator. |
| 4 | NC | unconnected | No connection. |
| 5 | AUTO RESET | input | Automatic reset input active low; logic 0 enables auto power-on reset circuit (requires VDD > 5V for reliable operation), logic 1 disables auto reset requiring positive MASTER RESET pulse to start counting. |
| 6 | MASTER RESET | input | Manual reset input active high; positive pulse resets 16-stage binary counter and output latch to high level; circuit is retriggerable. |
| 7 | VSS | power_in | Ground; negative power supply reference at 0V for all digital logic levels. |
| 8 | OUTPUT | output | Programmable frequency divider output selecting Q from counter stage selected by A/B inputs (8/10/13/16-stage); provides continuous f=fosc/2^N square wave at MODE=1 or single-transition pulse output at MODE=0. |
| 9 | Q/Q SELECT | input | Output polarity select input; logic 0 selects Q output initially low after reset, logic 1 selects Q̄ output initially high after reset. |
| 10 | MODE | input | Mode select input; logic 0 enables single-transition timer mode with output pulse after 2^(N-1) clock counts, logic 1 enables recycle mode with continuous f=fosc/2^N square wave output. |
| 11 | NC | unconnected | No connection. |
| 12 | A | input | Frequency select input A; combined with B input selects counter stage for frequency division factor: (A,B)=(0,0)→13-stage/8192, (0,1)→10-stage/1024, (1,0)→8-stage/256, (1,1)→16-stage/65536. |
| 13 | B | input | Frequency select input B; combined with A input selects counter stage for frequency divider ratio per frequency selection table. |
| 14 | VDD | power_in | Positive power supply; operating voltage 3V minimum to 18V typical, with 20V absolute maximum rating per JEDEC specification. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | DIP-14 |
| Category | Clock/Timing |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
CD4541BE - Footprint:
Package_DIP:DIP-14_W7.62mm - 3D model: DIP-14 (KiCad packages3D, STEP)
- 3D model files:
cd4541be-etched.step/cd4541be-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4541be.step/cd4541be.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (22 pp, sha256
1c648629cd0ba6ed, retrieved 2026-09-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).