component
CD4532BPWR
Public Made by Adomby adom
Texas Instruments Signal Switches, Multiplexers, Decoders, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD4532BPWR
Texas Instruments · Signal Switches, Multiplexers, Decoders · TSSOP-16
CD4532BPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | D4 | input | Priority input D4; D7 is highest priority and D0 lowest, with an input current of max ±1 µA at 18 V over the full temperature range. |
| 2 | D5 | input | Priority input D5, higher priority than D4 and lower than D6. |
| 3 | D6 | input | Priority input D6, higher priority than D5 and lower than D7. |
| 4 | D7 | input | Highest-priority input D7 of the 8-bit priority encoder. |
| 5 | EI | input | Chip-enable input; the encoder is inhibited when EI is low and encodes when EI is high. |
| 6 | Q2 | output | Binary code output bit 2 (MSB) of the highest-priority active input, valid when EI is high. |
| 7 | Q1 | output | Binary code output bit 1 of the highest-priority active input, valid when EI is high. |
| 8 | VSS | power_in | Ground (VSS) supply terminal; all voltages are referenced to it. |
| 9 | Q0 | output | Binary code output bit 0 (LSB) of the highest-priority active input, valid when EI is high. |
| 10 | D0 | input | Lowest-priority input D0 of the 8-bit priority encoder. |
| 11 | D1 | input | Priority input D1, higher priority than D0 and lower than D2. |
| 12 | D2 | input | Priority input D2, higher priority than D1 and lower than D3. |
| 13 | D3 | input | Priority input D3, higher priority than D2 and lower than D4. |
| 14 | GS | output | Group select output; goes high to indicate that priority inputs are present. |
| 15 | EO | output | Enable-out; high when no priority inputs are present, low if any input is high, disabling cascaded lower-order stages. |
| 16 | VDD | power_in | Positive supply voltage, recommended 3 V to 18 V, absolute maximum -0.5 V to +20 V referenced to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
CD4532BPWR - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
cd4532bpwr-etched.step/cd4532bpwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4532bpwr.step/cd4532bpwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (19 pp, sha256
306ddfe208da62a3, retrieved 2026-10-01, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).