CD4528SA16.TR

{
  "slug": "cd4528sa16-tr",
  "version": "0.1.0",
  "type": "component",
  "description": "Wuxi I core Elec Flip Flops, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic",
    "cd4528sa16.tr",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cd4528sa16-tr.kicad_sym",
    "cd4528sa16-tr.kicad_mod",
    "cd4528sa16-tr.glb",
    "cd4528sa16-tr.step",
    "cd4528sa16-tr.lbr",
    "docs/hero.png",
    "docs/cd4528sa16-tr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "cd4528sa16-tr-hero.glb",
    "cd4528sa16-tr-hero.overlay.json",
    "cd4528sa16-tr-etched.glb"
  ],
  "component": {
    "mpn": "CD4528SA16.TR",
    "manufacturer": "Wuxi I core Elec",
    "package": "SOP-16",
    "pin_count": 16,
    "category": "Logic",
    "subcategory": "Flip Flops",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590906157294960640",
    "parts": {
      "symbol": "cd4528sa16-tr.kicad_sym",
      "footprint": "cd4528sa16-tr.kicad_mod",
      "model_3d": "cd4528sa16-tr-hero.glb",
      "model_3d_plain": "cd4528sa16-tr-etched.glb",
      "model_3d_step": "cd4528sa16-tr-etched.step",
      "model_3d_step_plain": "cd4528sa16-tr.step",
      "lbr": "cd4528sa16-tr.lbr"
    },
    "distributor_links": {
      "lcsc": "C7425510"
    },
    "distributor_check": {
      "checked_at": "2026-10-20T17:45:25Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "no match"
      },
      "mouser": {
        "pn": null,
        "status": "no match"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "1CEXT",
        "type": "passive",
        "description": "External capacitor connection for monostable 1 that is always connected to ground; CEXT connects between this pin and 1REXT/CEXT."
      },
      {
        "number": "2",
        "name": "1REXT/CEXT",
        "type": "passive",
        "description": "External capacitor/resistor connection for monostable 1, where timing capacitor CEXT and timing resistor REXT (connected to VDD) set the output pulse duration."
      },
      {
        "number": "3",
        "name": "1CD",
        "type": "input",
        "description": "Clear direct input, active LOW; a LOW forces 1Q LOW and 1Q̅ HIGH and inhibits further pulses until the input returns HIGH."
      },
      {
        "number": "4",
        "name": "1B",
        "type": "input",
        "description": "Input triggered on a LOW-to-HIGH transition; when 1A̅ is HIGH, this transition produces an output pulse on 1Q."
      },
      {
        "number": "5",
        "name": "1A",
        "type": "input",
        "description": "Input triggered on a HIGH-to-LOW transition; when 1B is LOW, this transition produces an output pulse on 1Q (if 1CD̅ is HIGH)."
      },
      {
        "number": "6",
        "name": "1Q",
        "type": "output",
        "description": "Output of monostable 1, giving a positive LOW-HIGH-LOW pulse whose width is set by CEXT and REXT."
      },
      {
        "number": "7",
        "name": "1Q̅",
        "type": "output",
        "description": "Complementary output of monostable 1, active LOW, giving a negative HIGH-LOW-HIGH pulse when triggered."
      },
      {
        "number": "8",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground (0 V) reference for the device; all voltages are referenced to VSS."
      },
      {
        "number": "9",
        "name": "2Q̅",
        "type": "output",
        "description": "Complementary output of monostable 2, active LOW, giving a negative HIGH-LOW-HIGH pulse when triggered."
      },
      {
        "number": "10",
        "name": "2Q",
        "type": "output",
        "description": "Output of monostable 2, giving a positive LOW-HIGH-LOW pulse whose width is set by CEXT and REXT."
      },
      {
        "number": "11",
        "name": "2A",
        "type": "input",
        "description": "Input triggered on a HIGH-to-LOW transition; when 2B is LOW, this transition produces an output pulse on 2Q (if 2CD̅ is HIGH)."
      },
      {
        "number": "12",
        "name": "2B",
        "type": "input",
        "description": "Input triggered on a LOW-to-HIGH transition; when 2A̅ is HIGH, this transition produces an output pulse on 2Q."
      },
      {
        "number": "13",
        "name": "2CD",
        "type": "input",
        "description": "Clear direct input, active LOW; a LOW forces 2Q LOW and 2Q̅ HIGH and inhibits further pulses until the input returns HIGH."
      },
      {
        "number": "14",
        "name": "2REXT/CEXT",
        "type": "passive",
        "description": "External capacitor/resistor connection for monostable 2, where timing capacitor CEXT and timing resistor REXT (connected to VDD) set the output pulse duration."
      },
      {
        "number": "15",
        "name": "2CEXT",
        "type": "passive",
        "description": "External capacitor connection for monostable 2 that is always connected to ground; CEXT connects between this pin and 2REXT/CEXT."
      },
      {
        "number": "16",
        "name": "VDD",
        "type": "power_in",
        "description": "Supply voltage, recommended range 3 V to 12 V referenced to VSS."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The SOP16 variant is CD4528SA16.TR per the ordering table on page 3 (SOP16, 10.0mm×3.9mm, 1.27mm pit; Active-LOW overbars are printed as a separate dash in the extracted text; they were rendered here as; Pin types for the CEXT and REXT/CEXT pins (1, 2, 14, 15) are classed as passive based on their descr"
        ],
        "pages_sent": 14,
        "cost_usd": 0.0531,
        "at": "2026-10-20T17:43:27"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590906157294960640",
        "pages": 14,
        "sha256": "70d3bd5adeb1a320",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "cd4528sa16-tr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          9.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",
        "checked": "2026-10-20",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "cd4528sa16-tr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          9.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "36d5f9bc19aeeb2366b7951a521150cafff2167317b6e694803c7e2e59c116f6",
        "checked": "2026-10-20",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}