component

CD4528SA16.TR

Public Made by Adom

by adom

Wuxi I core Elec Flip Flops, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogiccd4528sa16.trfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
cd4528sa16-tr / README.md
History Download
Ray Publish 0.1.0 81c058a 9d ago

CD4528SA16.TR

Wuxi I core Elec · Flip Flops · SOP-16

CD4528SA16.TR from Wuxi I core Elec, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1CEXT passive External capacitor connection for monostable 1 that is always connected to ground; CEXT connects between this pin and 1REXT/CEXT.
2 1REXT/CEXT passive External capacitor/resistor connection for monostable 1, where timing capacitor CEXT and timing resistor REXT (connected to VDD) set the output pulse duration.
3 1CD input Clear direct input, active LOW; a LOW forces 1Q LOW and 1Q̅ HIGH and inhibits further pulses until the input returns HIGH.
4 1B input Input triggered on a LOW-to-HIGH transition; when 1A̅ is HIGH, this transition produces an output pulse on 1Q.
5 1A input Input triggered on a HIGH-to-LOW transition; when 1B is LOW, this transition produces an output pulse on 1Q (if 1CD̅ is HIGH).
6 1Q output Output of monostable 1, giving a positive LOW-HIGH-LOW pulse whose width is set by CEXT and REXT.
7 1Q̅ output Complementary output of monostable 1, active LOW, giving a negative HIGH-LOW-HIGH pulse when triggered.
8 VSS power_in Ground (0 V) reference for the device; all voltages are referenced to VSS.
9 2Q̅ output Complementary output of monostable 2, active LOW, giving a negative HIGH-LOW-HIGH pulse when triggered.
10 2Q output Output of monostable 2, giving a positive LOW-HIGH-LOW pulse whose width is set by CEXT and REXT.
11 2A input Input triggered on a HIGH-to-LOW transition; when 2B is LOW, this transition produces an output pulse on 2Q (if 2CD̅ is HIGH).
12 2B input Input triggered on a LOW-to-HIGH transition; when 2A̅ is HIGH, this transition produces an output pulse on 2Q.
13 2CD input Clear direct input, active LOW; a LOW forces 2Q LOW and 2Q̅ HIGH and inhibits further pulses until the input returns HIGH.
14 2REXT/CEXT passive External capacitor/resistor connection for monostable 2, where timing capacitor CEXT and timing resistor REXT (connected to VDD) set the output pulse duration.
15 2CEXT passive External capacitor connection for monostable 2 that is always connected to ground; CEXT connects between this pin and 2REXT/CEXT.
16 VDD power_in Supply voltage, recommended range 3 V to 12 V referenced to VSS.

Key specifications

Parameter Value
Manufacturer Wuxi I core Elec
Package SOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage (absolute maximum) VDD -0.5 14 V 6
DC input current IIK -10 10 mA any one input 6
input voltage VI -0.5 V all inputs; max printed as VDD+0.5 6
storage temperature Tstg -65 150 ℃ 6
total power dissipation Ptot 500 mW 6
device dissipation per output transistor P 100 mW per output transistor 6
soldering temperature TL 250 ℃ 10s, SOP 6
supply voltage (recommended) VDD 3 12 V 6
ambient temperature Tamb -40 85 ℃ in free air 6
supply current IDD 20 uA Tamb=25℃; /IO/=0 uA; VDD=5 V 7
supply current IDD 40 uA Tamb=25℃; /IO/=0 uA; VDD=10 V 7
LOW-level output current IOL 0.44 mA Tamb=25℃; VO=0.4 V; VDD=5 V 7
LOW-level output current IOL 1.1 mA Tamb=25℃; VO=0.5 V; VDD=10 V 7
HIGH-level output current IOH -1.4 mA Tamb=25℃; VO=2.5 V; VDD=5 V 7
HIGH-level output current IOH -0.44 mA Tamb=25℃; VO=4.6 V; VDD=5 V 7
HIGH-level output current IOH -1.1 mA Tamb=25℃; VO=9.5 V; VDD=10 V 7
LOW-level output voltage VOL 0.05 V Tamb=25℃; /IO/<1 uA; VDD=5 V 7
HIGH-level output voltage VOH 4.95 V Tamb=25℃; /IO/<1 uA; VDD=5 V 7
HIGH-level output voltage VOH 9.95 V Tamb=25℃; /IO/<1 uA; VDD=10 V 7
LOW-level input voltage VIL 1.5 V Tamb=25℃; /IO/<1 uA; VDD=5 V 7
LOW-level input voltage VIL 3 V Tamb=25℃; /IO/<1 uA; VDD=10 V 7
HIGH-level input voltage VIH 3.5 V Tamb=25℃; /IO/<1 uA; VDD=5 V 7
HIGH-level input voltage VIH 7 V Tamb=25℃; /IO/<1 uA; VDD=10 V 7
input leakage current II -0.3 0.3 uA Tamb=25℃; VDD=12 V 7
supply current IDD 150 uA Tamb=+85℃; /IO/=0 uA; VDD=5 V 7
supply current IDD 300 uA Tamb=+85℃; /IO/=0 uA; VDD=10 V 7
LOW-level output current IOL 0.52 mA Tamb=-40℃; VO=0.4 V; VDD=5 V 7
LOW-level output current IOL 0.36 mA Tamb=+85℃; VO=0.4 V; VDD=5 V 7
LOW-level output current IOL 1.3 mA Tamb=-40℃; VO=0.5 V; VDD=10 V 7
LOW-level output current IOL 0.9 mA Tamb=+85℃; VO=0.5 V; VDD=10 V 7
HIGH-level output current IOH -1.7 mA Tamb=-40℃; VO=2.5 V; VDD=5 V 7
HIGH-level output current IOH -0.52 mA Tamb=-40℃; VO=4.6 V; VDD=5 V 7
HIGH-level output current IOH -0.36 mA Tamb=+85℃; VO=4.6 V; VDD=5 V 7
HIGH-level output current IOH -1.3 mA Tamb=-40℃; VO=9.5 V; VDD=10 V 7
HIGH-level output current IOH -0.9 mA Tamb=+85℃; VO=9.5 V; VDD=10 V 7
input leakage current II -1 1 uA Tamb=+85℃; VDD=12 V 7
HIGH to LOW propagation delay tPHL 140 280 ns nA or nB to nQ; see Figure 5; VDD=5V 8
HIGH to LOW propagation delay tPHL 50 100 ns nA or nB to nQ; see Figure 5; VDD=10V 8
input capacitance CI 7.5 pF 8

CAD (KiCad official)

  • Symbol: CD4528SA16.TR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: cd4528sa16-tr-etched.step / cd4528sa16-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4528sa16-tr.step / cd4528sa16-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Wuxi I core Elec datasheet (14 pp, sha256 70d3bd5adeb1a320, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF