component
CD4528BM
Public Made by Adomby adom
HGSEMI Monostable Multivibrators, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
Ray
cd4528bm: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding)
42d98dd
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255
{
"schema_version": 1,
"type": "component",
"slug": "cd4528bm",
"title": "CD4528BM",
"brief": "HGSEMI Monostable Multivibrators, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"version": "0.1.0",
"license": "CC-BY-SA-4.0",
"tags": [
"component",
"logic",
"cd4528bm",
"factory-2.0.0",
"extractor-text"
],
"component": {
"mpn": "CD4528BM",
"manufacturer": "HGSEMI",
"package": "SOP-16",
"pin_count": 16,
"category": "Logic",
"subcategory": "Monostable Multivibrators",
"datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603359643905241088",
"parts": {
"symbol": "cd4528bm.kicad_sym",
"footprint": "cd4528bm.kicad_mod",
"model_3d": "cd4528bm-etched.glb",
"model_3d_plain": "cd4528bm.glb",
"model_3d_step": "cd4528bm-etched.step",
"model_3d_step_plain": "cd4528bm.step",
"lbr": "cd4528bm.lbr"
},
"distributor_links": {
"lcsc": "C22446574"
},
"pins": [
{
"number": "1",
"name": "T1A",
"type": "passive",
"description": "External timing capacitor Cx bottom terminal for monostable A; datasheet note states this pin must be connected externally to VSS (pin 8)."
},
{
"number": "2",
"name": "T2A",
"type": "passive",
"description": "External RC timing node for monostable A; Rx is connected from VDD to this pin and Cx between this pin and T1A to set output pulse width per PWout = 0.2·Rx·Cx·ln(VDD−VSS)."
},
{
"number": "3",
"name": "CDA",
"type": "input",
"description": "Active-low asynchronous clear/reset input for monostable A; a LOW level forces QA LOW and Q̄A HIGH regardless of trigger input states."
},
{
"number": "4",
"name": "AA",
"type": "input",
"description": "Positive-edge-sensitive trigger input A for monostable A; a LOW-to-HIGH transition initiates the output pulse when CD is HIGH and B input is HIGH."
},
{
"number": "5",
"name": "AB",
"type": "input",
"description": "Negative-edge-sensitive trigger input B for monostable A; a HIGH-to-LOW transition initiates the output pulse when CD is HIGH and A input is LOW."
},
{
"number": "6",
"name": "QA",
"type": "output",
"description": "Non-inverting monostable pulse output for circuit A; HIGH pulse width is determined by external Rx and Cx timing components; VOH min 4.95 V at VDD = 5 V."
},
{
"number": "7",
"name": "/QA",
"type": "output",
"description": "Complementary inverting monostable pulse output for circuit A; LOW pulse is concurrent with QA HIGH pulse; VOL max 0.05 V at VDD = 5 V."
},
{
"number": "8",
"name": "VSS",
"type": "power_in",
"description": "Negative supply / ground reference; defined as 0 V; timing capacitor terminals T1A and T1B must be connected here externally."
},
{
"number": "9",
"name": "/QB",
"type": "output",
"description": "Complementary inverting monostable pulse output for circuit B; LOW pulse is concurrent with QB HIGH pulse; VOL max 0.05 V at VDD = 5 V."
},
{
"number": "10",
"name": "QB",
"type": "output",
"description": "Non-inverting monostable pulse output for circuit B; HIGH pulse width is determined by external Rx and Cx timing components; VOH min 4.95 V at VDD = 5 V."
},
{
"number": "11",
"name": "BB",
"type": "input",
"description": "Negative-edge-sensitive trigger input B for monostable B; a HIGH-to-LOW transition initiates the output pulse when CD is HIGH and A input is LOW."
},
{
"number": "12",
"name": "BA",
"type": "input",
"description": "Positive-edge-sensitive trigger input A for monostable B; a LOW-to-HIGH transition initiates the output pulse when CD is HIGH and B input is HIGH."
},
{
"number": "13",
"name": "CDB",
"type": "input",
"description": "Active-low asynchronous clear/reset input for monostable B; a LOW level forces QB LOW and Q̄B HIGH regardless of trigger input states."
},
{
"number": "14",
"name": "T2B",
"type": "passive",
"description": "External RC timing node for monostable B; Rx is connected from VDD to this pin and Cx between this pin and T1B to set output pulse width per PWout = 0.2·Rx·Cx·ln(VDD−VSS)."
},
{
"number": "15",
"name": "T1B",
"type": "passive",
"description": "External timing capacitor Cx bottom terminal for monostable B; datasheet note states this pin must be connected externally to VSS (pin 8)."
},
{
"number": "16",
"name": "VDD",
"type": "power_in",
"description": "Positive supply voltage; recommended operating range 3 V to 15 V, absolute maximum 18 V; quiescent current typ. 5 nA/package at 5 V."
}
],
"provenance": {
"extractor": "extract_pins 0.2",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.2",
"primary_model": "claude-sonnet-4-6",
"primary_mode": "text+vision",
"consensus_model": "claude-opus-4-7",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"vision extraction: provenance cannot be text-verified; needs consensus"
],
"pages_sent": 11,
"cost_usd": 0.4563,
"at": "2026-09-17T22:05:26"
},
"datasheet": {
"url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603359643905241088",
"pages": 11,
"sha256": "ceca0343149c8755",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 16,
"described": 16,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "cd4528bm.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6,
9.9,
1.75
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",
"checked": "2026-10-07",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "cd4528bm-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6,
9.9,
1.75
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "ad4c9e43ade5ae68ee0381202b9503c3a7469736f0759cc023c1be3bf96841cd",
"checked": "2026-10-07",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
},
"metadata": {
"specs": {
"Manufacturer": "HGSEMI",
"Package": "SOP-16",
"Category": "Logic",
"Pins": "16"
}
},
"variants": [],
"sections": [
"hero",
"viewers",
"readme",
"breadcrumbs",
"info"
],
"discovery_triggers": [
"cd4528bm"
],
"discovery_pitch": "CD4528BM (HGSEMI) component page with datasheet-verified CAD.",
"author": {
"name": "Ray"
},
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"cd4528bm.kicad_sym",
"cd4528bm.kicad_mod",
"cd4528bm.glb",
"cd4528bm.step",
"cd4528bm.lbr",
"docs/hero.png",
"docs/cd4528bm-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html"
],
"visibility": {
"public": true
},
"updated_at": "2026-09-24T18:51:39.619Z"
}