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CD4528BM

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HGSEMI Monostable Multivibrators, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD4528BM

HGSEMI · Monostable Multivibrators · SOP-16

CD4528BM from HGSEMI, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 T1A passive External timing capacitor Cx bottom terminal for monostable A; datasheet note states this pin must be connected externally to VSS (pin 8).
2 T2A passive External RC timing node for monostable A; Rx is connected from VDD to this pin and Cx between this pin and T1A to set output pulse width per PWout = 0.2·Rx·Cx·ln(VDD−VSS).
3 CDA input Active-low asynchronous clear/reset input for monostable A; a LOW level forces QA LOW and Q̄A HIGH regardless of trigger input states.
4 AA input Positive-edge-sensitive trigger input A for monostable A; a LOW-to-HIGH transition initiates the output pulse when CD is HIGH and B input is HIGH.
5 AB input Negative-edge-sensitive trigger input B for monostable A; a HIGH-to-LOW transition initiates the output pulse when CD is HIGH and A input is LOW.
6 QA output Non-inverting monostable pulse output for circuit A; HIGH pulse width is determined by external Rx and Cx timing components; VOH min 4.95 V at VDD = 5 V.
7 /QA output Complementary inverting monostable pulse output for circuit A; LOW pulse is concurrent with QA HIGH pulse; VOL max 0.05 V at VDD = 5 V.
8 VSS power_in Negative supply / ground reference; defined as 0 V; timing capacitor terminals T1A and T1B must be connected here externally.
9 /QB output Complementary inverting monostable pulse output for circuit B; LOW pulse is concurrent with QB HIGH pulse; VOL max 0.05 V at VDD = 5 V.
10 QB output Non-inverting monostable pulse output for circuit B; HIGH pulse width is determined by external Rx and Cx timing components; VOH min 4.95 V at VDD = 5 V.
11 BB input Negative-edge-sensitive trigger input B for monostable B; a HIGH-to-LOW transition initiates the output pulse when CD is HIGH and A input is LOW.
12 BA input Positive-edge-sensitive trigger input A for monostable B; a LOW-to-HIGH transition initiates the output pulse when CD is HIGH and B input is HIGH.
13 CDB input Active-low asynchronous clear/reset input for monostable B; a LOW level forces QB LOW and Q̄B HIGH regardless of trigger input states.
14 T2B passive External RC timing node for monostable B; Rx is connected from VDD to this pin and Cx between this pin and T1B to set output pulse width per PWout = 0.2·Rx·Cx·ln(VDD−VSS).
15 T1B passive External timing capacitor Cx bottom terminal for monostable B; datasheet note states this pin must be connected externally to VSS (pin 8).
16 VDD power_in Positive supply voltage; recommended operating range 3 V to 15 V, absolute maximum 18 V; quiescent current typ. 5 nA/package at 5 V.

Key specifications

Parameter Value
Manufacturer HGSEMI
Package SOP-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: CD4528BM
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: cd4528bm-etched.step / cd4528bm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4528bm.step / cd4528bm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HGSEMI datasheet (11 pp, sha256 ceca0343149c8755, retrieved 2026-09-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-sonnet-4-6 (text+vision), consensus claude-opus-4-7 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF