component
CD4522BE
Public Made by Adomby adom
Texas Instruments Counters, Dividers, PDIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CD4522BE
Texas Instruments · Counters, Dividers · PDIP-16
CD4522BE from Texas Instruments, in a PDIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q3 | output | BCD counter output Q3 (most significant bit). |
| 2 | P3 | input | Preset data input P3, loaded into the counter when Preset Enable is high. |
| 3 | PRESET ENABLE | input | Preset Enable input; a high level presets the counter to the P0-P3 value, and the "0" output is tied to it in single-stage divide-by-N operation. |
| 4 | CLOCK INHIBIT | input | Clock Inhibit input; a HIGH disables the pulse-counting function, and a negative transition on it counts down when Clock is high. |
| 5 | P0 | input | Preset data input P0 (least significant bit), loaded when Preset Enable is high. |
| 6 | CLOCK | input | Clock input; the counter decrements on the positive Clock transition. |
| 7 | Q0 | output | BCD counter output Q0 (least significant bit). |
| 8 | VSS | power_in | Ground (VSS) supply terminal, pin 8. |
| 9 | Q1 | output | BCD counter output Q1. |
| 10 | MASTER RESET | input | Master Reset input; a HIGH asynchronously resets the divide-by-N operation. |
| 11 | P1 | input | Preset data input P1, loaded when Preset Enable is high. |
| 12 | "0" | output | Decoded "0" state output used for divide-by-N applications. |
| 13 | CASCADE FEEDBACK | input | Cascade Feedback input that allows multiple-stage divide-by-N operation without external gating. |
| 14 | P2 | input | Preset data input P2, loaded when Preset Enable is high. |
| 15 | Q2 | output | BCD counter output Q2. |
| 16 | VDD | power_in | Positive supply (VDD), pin 16; recommended range 3 V to 18 V, absolute maximum -0.5 V to +20 V referenced to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
CD4522BE - Footprint:
Package_DIP:DIP-16_W7.62mm - 3D model: PDIP-16 (KiCad packages3D, STEP)
- 3D model files:
cd4522be-etched.step/cd4522be-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4522be.step/cd4522be.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (16 pp, sha256
307075b020a7afab, retrieved 2026-10-16, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CD4522BE
**Texas Instruments** · Counters, Dividers · PDIP-16
CD4522BE from Texas Instruments, in a PDIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q3 | output | BCD counter output Q3 (most significant bit). |
| 2 | P3 | input | Preset data input P3, loaded into the counter when Preset Enable is high. |
| 3 | PRESET ENABLE | input | Preset Enable input; a high level presets the counter to the P0-P3 value, and the "0" output is tied to it in single-stage divide-by-N operation. |
| 4 | CLOCK INHIBIT | input | Clock Inhibit input; a HIGH disables the pulse-counting function, and a negative transition on it counts down when Clock is high. |
| 5 | P0 | input | Preset data input P0 (least significant bit), loaded when Preset Enable is high. |
| 6 | CLOCK | input | Clock input; the counter decrements on the positive Clock transition. |
| 7 | Q0 | output | BCD counter output Q0 (least significant bit). |
| 8 | VSS | power_in | Ground (VSS) supply terminal, pin 8. |
| 9 | Q1 | output | BCD counter output Q1. |
| 10 | MASTER RESET | input | Master Reset input; a HIGH asynchronously resets the divide-by-N operation. |
| 11 | P1 | input | Preset data input P1, loaded when Preset Enable is high. |
| 12 | "0" | output | Decoded "0" state output used for divide-by-N applications. |
| 13 | CASCADE FEEDBACK | input | Cascade Feedback input that allows multiple-stage divide-by-N operation without external gating. |
| 14 | P2 | input | Preset data input P2, loaded when Preset Enable is high. |
| 15 | Q2 | output | BCD counter output Q2. |
| 16 | VDD | power_in | Positive supply (VDD), pin 16; recommended range 3 V to 18 V, absolute maximum -0.5 V to +20 V referenced to VSS. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-16 |
| Category | Logic |
| Pins | 16 |
## CAD (KiCad official)
- Symbol: `CD4522BE`
- Footprint: `Package_DIP:DIP-16_W7.62mm`
- 3D model: PDIP-16 (KiCad packages3D, STEP)
- 3D model files: `cd4522be-etched.step` / `cd4522be-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4522be.step` / `cd4522be.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd4522b) (16 pp, sha256 `307075b020a7afab`, retrieved 2026-10-16, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cd4522be-datasheet.pdf)