component
CD4520NS16ARDQ
Public Made by Adomby adom
GR Counters, Dividers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# CD4520NS16ARDQ++**GR** · Counters, Dividers · SOP-16++CD4520NS16ARDQ from GR, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CLOCK_A | input | Clock input for counter A; increments on positive-going transition when ENABLE A is held high. |+| 2 | ENABLE_A | input | Enable input for counter A; held high for CLOCK-triggered counting; counter also increments on negative-going transition of ENABLE when CLOCK A is held high. |+| 3 | Q1A | output | Binary count output bit 1 (LSB) for counter A; VOH min 4.95 V at VDD=5 V, VOL max 0.05 V. |+| 4 | Q2A | output | Binary count output bit 2 for counter A; VOH min 4.95 V at VDD=5 V, VOL max 0.05 V. |+| 5 | Q3A | output | Binary count output bit 3 for counter A; VOH min 4.95 V at VDD=5 V, VOL max 0.05 V. |+| 6 | Q4A | output | Binary count output bit 4 (MSB) for counter A; connect to ENABLE B for ripple cascading. |+| 7 | RESET_A | input | Active-high asynchronous reset for counter A; high level forces Q1A-Q4A to 0 regardless of clock. |+| 8 | VSS | power_in | Negative supply / ground reference, 0 V. |+| 9 | CLOCK_B | input | Clock input for counter B; increments on positive-going transition when ENABLE B is held high. |+| 10 | ENABLE_B | input | Enable input for counter B; held high for CLOCK-triggered counting; counter also increments on negative-going transition of ENABLE when CLOCK B is held high. |+| 11 | Q1B | output | Binary count output bit 1 (LSB) for counter B; VOH min 4.95 V at VDD=5 V, VOL max 0.05 V. |+| 12 | Q2B | output | Binary count output bit 2 for counter B; VOH min 4.95 V at VDD=5 V, VOL max 0.05 V. |+| 13 | Q3B | output | Binary count output bit 3 for counter B; VOH min 4.95 V at VDD=5 V, VOL max 0.05 V. |+| 14 | Q4B | output | Binary count output bit 4 (MSB) for counter B; connect to ENABLE of next stage for ripple cascading. |+| 15 | RESET_B | input | Active-high asynchronous reset for counter B; high level forces Q1B-Q4B to 0 regardless of clock. |+| 16 | VDD | power_in | Positive supply voltage; operating range up to 20 V absolute maximum; quiescent current 1 µA max at 18 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | GR |+| Package | SOP-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `CD4520NS16ARDQ`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOP-16 (KiCad packages3D, STEP)+- 3D model files: `cd4520ns16ardq-etched.step` / `cd4520ns16ardq-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4520ns16ardq.step` / `cd4520ns16ardq.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [GR datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603351089303736320) (9 pp, sha256 `7926a4d7a9b4e40b`, retrieved 2026-09-22, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-sonnet-4-6` (text+vision), consensus `claude-opus-4-7` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd4520ns16ardq-datasheet.pdf)
page.jsonadded+191@@ -0,0 +1,191 @@+{+ "slug": "cd4520ns16ardq",+ "version": "0.1.0",+ "type": "component",+ "description": "GR Counters, Dividers, SOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "cd4520ns16ardq",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cd4520ns16ardq.kicad_sym",+ "cd4520ns16ardq.kicad_mod",+ "cd4520ns16ardq.glb",+ "cd4520ns16ardq.step",+ "cd4520ns16ardq.lbr",+ "docs/hero.png",+ "docs/cd4520ns16ardq-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "CD4520NS16ARDQ",+ "manufacturer": "GR",+ "package": "SOP-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Counters, Dividers",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603351089303736320",+ "parts": {+ "symbol": "cd4520ns16ardq.kicad_sym",+ "footprint": "cd4520ns16ardq.kicad_mod",+ "model_3d": "cd4520ns16ardq-etched.glb",+ "model_3d_plain": "cd4520ns16ardq.glb",+ "model_3d_step": "cd4520ns16ardq-etched.step",+ "model_3d_step_plain": "cd4520ns16ardq.step",+ "lbr": "cd4520ns16ardq.lbr"+ },+ "distributor_links": {+ "lcsc": "C22465478"+ },+ "pins": [+ {+ "number": "1",+ "name": "CLOCK_A",+ "type": "input",+ "description": "Clock input for counter A; increments on positive-going transition when ENABLE A is held high."+ },+ {+ "number": "2",+ "name": "ENABLE_A",+ "type": "input",+ "description": "Enable input for counter A; held high for CLOCK-triggered counting; counter also increments on negative-going transition of ENABLE when CLOCK A is held high."+ },+ {+ "number": "3",+ "name": "Q1A",+ "type": "output",+ "description": "Binary count output bit 1 (LSB) for counter A; VOH min 4.95 V at VDD=5 V, VOL max 0.05 V."+ },+ {+ "number": "4",+ "name": "Q2A",+ "type": "output",+ "description": "Binary count output bit 2 for counter A; VOH min 4.95 V at VDD=5 V, VOL max 0.05 V."+ },+ {+ "number": "5",+ "name": "Q3A",+ "type": "output",+ "description": "Binary count output bit 3 for counter A; VOH min 4.95 V at VDD=5 V, VOL max 0.05 V."+ },+ {+ "number": "6",+ "name": "Q4A",+ "type": "output",+ "description": "Binary count output bit 4 (MSB) for counter A; connect to ENABLE B for ripple cascading."+ },+ {+ "number": "7",+ "name": "RESET_A",+ "type": "input",+ "description": "Active-high asynchronous reset for counter A; high level forces Q1A-Q4A to 0 regardless of clock."+ },+ {+ "number": "8",+ "name": "VSS",+ "type": "power_in",+ "description": "Negative supply / ground reference, 0 V."+ },+ {+ "number": "9",+ "name": "CLOCK_B",+ "type": "input",+ "description": "Clock input for counter B; increments on positive-going transition when ENABLE B is held high."+ },+ {+ "number": "10",+ "name": "ENABLE_B",+ "type": "input",+ "description": "Enable input for counter B; held high for CLOCK-triggered counting; counter also increments on negative-going transition of ENABLE when CLOCK B is held high."+ },+ {+ "number": "11",+ "name": "Q1B",+ "type": "output",+ "description": "Binary count output bit 1 (LSB) for counter B; VOH min 4.95 V at VDD=5 V, VOL max 0.05 V."+ },+ {+ "number": "12",+ "name": "Q2B",+ "type": "output",+ "description": "Binary count output bit 2 for counter B; VOH min 4.95 V at VDD=5 V, VOL max 0.05 V."+ },+ {+ "number": "13",+ "name": "Q3B",+ "type": "output",+ "description": "Binary count output bit 3 for counter B; VOH min 4.95 V at VDD=5 V, VOL max 0.05 V."+ },+ {+ "number": "14",+ "name": "Q4B",+ "type": "output",+ "description": "Binary count output bit 4 (MSB) for counter B; connect to ENABLE of next stage for ripple cascading."+ },+ {+ "number": "15",+ "name": "RESET_B",+ "type": "input",+ "description": "Active-high asynchronous reset for counter B; high level forces Q1B-Q4B to 0 regardless of clock."+ },+ {+ "number": "16",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply voltage; operating range up to 20 V absolute maximum; quiescent current 1 µA max at 18 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-sonnet-4-6",+ "primary_mode": "text+vision",+ "consensus_model": "claude-opus-4-7",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "vision extraction: provenance cannot be text-verified; needs consensus"+ ],+ "pages_sent": 9,+ "cost_usd": 0.2862,+ "at": "2026-09-22T00:31:43"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603351089303736320",+ "pages": 9,+ "sha256": "7926a4d7a9b4e40b",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}