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CD4520NS16ARDQ

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GR Counters, Dividers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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CD4520NS16ARDQ

GR · Counters, Dividers · SOP-16

CD4520NS16ARDQ from GR, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLOCK_A input Clock input for counter A; increments on positive-going transition when ENABLE A is held high.
2 ENABLE_A input Enable input for counter A; held high for CLOCK-triggered counting; counter also increments on negative-going transition of ENABLE when CLOCK A is held high.
3 Q1A output Binary count output bit 1 (LSB) for counter A; VOH min 4.95 V at VDD=5 V, VOL max 0.05 V.
4 Q2A output Binary count output bit 2 for counter A; VOH min 4.95 V at VDD=5 V, VOL max 0.05 V.
5 Q3A output Binary count output bit 3 for counter A; VOH min 4.95 V at VDD=5 V, VOL max 0.05 V.
6 Q4A output Binary count output bit 4 (MSB) for counter A; connect to ENABLE B for ripple cascading.
7 RESET_A input Active-high asynchronous reset for counter A; high level forces Q1A-Q4A to 0 regardless of clock.
8 VSS power_in Negative supply / ground reference, 0 V.
9 CLOCK_B input Clock input for counter B; increments on positive-going transition when ENABLE B is held high.
10 ENABLE_B input Enable input for counter B; held high for CLOCK-triggered counting; counter also increments on negative-going transition of ENABLE when CLOCK B is held high.
11 Q1B output Binary count output bit 1 (LSB) for counter B; VOH min 4.95 V at VDD=5 V, VOL max 0.05 V.
12 Q2B output Binary count output bit 2 for counter B; VOH min 4.95 V at VDD=5 V, VOL max 0.05 V.
13 Q3B output Binary count output bit 3 for counter B; VOH min 4.95 V at VDD=5 V, VOL max 0.05 V.
14 Q4B output Binary count output bit 4 (MSB) for counter B; connect to ENABLE of next stage for ripple cascading.
15 RESET_B input Active-high asynchronous reset for counter B; high level forces Q1B-Q4B to 0 regardless of clock.
16 VDD power_in Positive supply voltage; operating range up to 20 V absolute maximum; quiescent current 1 µA max at 18 V.

Key specifications

Parameter Value
Manufacturer GR
Package SOP-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: CD4520NS16ARDQ
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: cd4520ns16ardq-etched.step / cd4520ns16ardq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4520ns16ardq.step / cd4520ns16ardq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: GR datasheet (9 pp, sha256 7926a4d7a9b4e40b, retrieved 2026-09-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-sonnet-4-6 (text+vision), consensus claude-opus-4-7 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF